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Posts Tagged ‘In-Design’

Custom Compiler at DAC 2016

Monday, August 8th, 2016

DAC 2016 saw the first Synopsys custom design luncheon to feature Custom Compiler. It was a sold out event with 150 customer attendees eager to hear from Synopsys and other customers about how Synopsys is progressing in the custom design space. Antun Domic, Executive VP and General Manager of Synopsys’ Design Group moderated the event which included speakers from STMicroelectronics, GSI Technology, Samsung Foundry and the Synopsys IP team. For those of you who missed the live event, following is a short summary of the event highlights.


Antun opened the proceedings and presented Synopsys’ fresh approach to custom layout with Custom Compiler. He shared details of the pioneering visually-assisted automation technologies that speed up custom design tasks, reduce iterations and enable reuse.

Antun then went on to introduce each of the customer speakers who related their experiences using Custom Compiler and how visually-assisted automation helped them reduce their layout efforts from days to hours.


Custom Compiler In-Design Assistants (Part 2)

Thursday, July 14th, 2016

Planning which metal shape goes on which color (mask) is key when designing in a FinFET process, especially when propagating connections through the layout hierarchy. In addition, highly matched signals such as complementary clocks must be assigned to the same color, as routes on different masks have different resistances. So how do we ensure we are keeping things in order with respect to the matching of resistance and capacitance?

Custom Compiler’s In-Design assistants include a built-in engine that computes resistance of a net from a single source to a single destination or multiple destinations. It is an interactive tool that can be run often during the layout process, has a simple use model and a fast response time. To report the resistance of a net, the layout engineer simply selects the net of interest from either the layout, the design navigator or the schematic. The next step is to invoke the resistance report command which pops up in the electrical report menu. The report type is set to “Resistance” and the source and destination points are entered.  The report is run and the results are populated in the Electrical Reporter pane.

S2C: FPGA Base prototyping- Download white paper

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