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Posts Tagged ‘EM’

Custom Compiler In-Design Assistants (Part 3)

Tuesday, September 20th, 2016

In the blog ‘Custom Compiler In-Design Assistants (Part 2)’, I outlined how we can use StarRC to report capacitances on critical nets in the layout even when the design is still in flux and not completely LVS-clean. In addition to capacitance reports, we also showed resistance reporting which is critical for FinFET-based layouts. At advanced nodes, the impact of parasitics, electromigration (EM) and restricted design rules drive critical layout choices. Interconnect that does not meet resistance, or EM criteria and unbalanced capacitances on matched nets, can and often does adversely impact layout schedules. So the earlier in the layout phase the layout engineer can address these issues, the sooner he or she can close the design.

EM in particular is a notorious problem in the FinFET process due to the high drive of the transistors and thin metals. So let’s say, for example, the layout engineer has to route a critical net which could be susceptible to the impact of EM. This is a non-trivial task that could be quite challenging. However, if you use Custom Compiler, there are some very cool capabilities that make laying out interconnect that meets EM criteria very quick and very easy.

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Current Solutions for FinFET (Part 3)

Friday, April 29th, 2016

What is electromigration (EM) and why is it something we should care about?

Here’s the definition of electromigration from Wikipedia: “Electromigration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms.”

Put simply, when the current density gets too high for a given wire width, you get problems. These problems manifest themselves in two ways, either a void in the metal wire that creates an open circuit or a hillock that creates a short to another wire. Either way your chip fails. Electromigration is made worse by temperature and mechanical stresses.

em

Electromigration in the FinFET process is now a first-order effect and has a huge impact on the Mean Time To Failure (MTTF) of a metal wire. So, as you can imagine, to ensure you have a robust design that will last, great care has to be taken when choosing wire widths for interconnect and power grids.
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Hurricane FinFET (Part 3)

Friday, March 18th, 2016

Continuing on the theme of FinFET layout, let’s consider what you have to do for routing. Again drawing on the experience of my layout colleagues who are still ‘in the business’ and dealing with FinFETs, here are a few landmines you will have to deal with.

One particular issue they encounter is that although the base layers have shrunk considerably, the shrink of the routing layers has not kept pace. Each new node has brought us smaller transistors, but the minimum metal pitch has not really changed. This really impacts layout floorplanning because designs that were once dictated by device area are now dictated by the ability to route the required signals. Double-/triple-patterning compounds the issue even further.
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