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Posts Tagged ‘digital cell layout’

Rapid Custom Digital Cell Layout with the Symbolic Editor

Thursday, November 3rd, 2016

In the ‘Custom Compiler Layout AssistantsĀ (Part 1)’ blog post, IĀ profiled the use of the symbolic editor and how it makes placing devices that need to be in a specific interdigitated pattern (for example, a differential pair) very easy. With no constraints to enter and no code to write, layout is done in minutes vs. hours.

However, there is a lot more to the symbolic editor than the ability to simplify interdigitation. One good example is the ability to define multiple P and N row pairs and then symbolically chain and fold the transistors such that you get them to fit neatly in the rows. This is a key feature that allows you to not only control the aspect ratio of the design, but to very rapidly create a custom digital cell layout, as shown in Figure 1.

SED_Multi_2_croppped

Figure 1. Multiple Row Pairs

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