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Posts Tagged ‘differential pair’

Reducing Analog Cell Layout Time with the Symbolic Editor

Thursday, December 1st, 2016

Hello again!

In the last blog post I profiled the use of Custom Compiler’s Symbolic Editor for rapid digital cell layout.

In this post, we will tackle analog cell layout and show some more of the Symbolic Editor features that enable analog layout engineers to complete their layout in minutes vs. hours.

As with the digital cell layout, engineers can take advantage of the Symbolic Editor’s ability to define multiple P and N row pairs, as shown in Figure 1.

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Figure 1. Multiple Row Pairs

The preview window shows how the layout will look when realized on the layout canvas. In this example, it is clear that in order to make the design more compact, the larger transistors need to be folded.

Folding the transistors is very easy using the Symbolic Editor. Options on the toolbar allow the designer to fold the transistor by specifying either the number of segments desired or by specifying a width threshold. Once the option is set, all the layout engineer has to do is simply select the appropriate devices and have them folded such that the transistors fit neatly in the rows. Figure 2 shows how the design looks before and after folding.

 

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Figure 2. Before and After Folding

Analog designs are very sensitive to process variation, noise and other manufacturing variances. In order to mitigate the impact of these variances on critical pieces of circuitry, layout engineers use complex interdigitation patterns in addition to other layout techniques. This is a critical practice for analog design, because the effects of the variances, if not accounted for, can lead to a non-functioning piece of circuitry.

The Symbolic Editor provides a simple way to implement these complex patterns via the Pattern Generator. As well as being able to specify your own patterns, the Pattern Generator also includes a library of built-in patterns that can be used to interdigitate devices in a specific order. Take a differential pair, for example. The layout engineer can choose from a variety of different patterns as shown in Figure 3.

 

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Figure 3. Pattern Generator

The preview window makes it easy to see how the layout will look with the chosen pattern and, once the engineer is happy with the choice, s/he simply realizes the layout on the canvas. Figure 4 shows the results of choosing a Common Centroid pattern. With no constraints to enter, no code to write, layout is done in minutes vs. hours.

 

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Figure 4. Highlighted Devices as Part of a Common Centroid Pattern

Transistors are not the only devices that can take advantage of the Symbolic Editor. In the automotive world, it is often necessary to lay out banks of resistors. This is something the Symbolic Editor can also help with. Resistors can be chained serially in a variety of different routing patterns.

Using the Symbolic Editor allows the layout engineer to make simple graphical choices of how the layout needs to look and then have the detailed placement taken care of by the placement engine. It makes it easy to add or remove placement rows and columns, as well as insert dummy devices. Figure 6 shows the completed symbolic layout of two resistor banks with automatic insertion of dummies.

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Figure 6. Completed Symbolic Layout of Two Resistor Banks with Automatic Insertion of Dummies

Generating devices and placing them such that they meet all the design rules and produce a robust working design is about 30% of the time spent doing layout. Using a layout assistant like the Symbolic Editor really speeds this task up and makes the layout engineer much more productive. Synopsys has invested heavily in this technology over a period of 5+ years, such that we can address a broad range of design applications, unlike the recent offerings from other EDA vendors. Applicable to both FinFET and established planar CMOS nodes, the Symbolic Editor makes analog cell layout quick and easy.

To learn more about how the Symbolic Editor can help to rapidly create analog cells, check out Custom Compiler Webisode #6 that shows the Symbolic Editor in action.

Custom Compiler Layout Assistants (Part 1)

Wednesday, June 1st, 2016

As mentioned previously, on March 30th Silicon Valley was buzzing with excitement. Synopsys revealed Custom Compiler, a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations and enable reuse at the SNUG Silicon Valley event. During this event, the R&D folks did a walkthrough of the technology ‘under-the-hood’ and showed the audience some cool layout assistants that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints. [Click here to view the videolog of the SNUG event.]

One of the layout assistants that was shown was the symbolic editor. This really is a must-have assistant when it comes to placing devices that need to be in a specific interdigitated pattern, like a differential pair. In the schematic, it is two symbols, but in the layout it could be hundreds of devices. The symbolic editor allows device placement to be edited in an easy and graphical manner and comes with a rich collection of predefined placement patterns. If you find a placement pattern you like, you can simply use it as-is and the symbolic editor will generate a correct-by-construction placement that you can instantiate in your layout. If you don’t find an exact match, you can easily use a pattern that is similar to what you need and rearrange the placement pattern graphically. No constraints to enter, no code to write and layout is done in minutes vs. hours.
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