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Posts Tagged ‘Custom Compiler’

Reducing Analog Cell Layout Time with the Symbolic Editor

Thursday, December 1st, 2016

Hello again!

In the last blog post I profiled the use of Custom Compiler’s Symbolic Editor for rapid digital cell layout.

In this post, we will tackle analog cell layout and show some more of the Symbolic Editor features that enable analog layout engineers to complete their layout in minutes vs. hours.

As with the digital cell layout, engineers can take advantage of the Symbolic Editor’s ability to define multiple P and N row pairs, as shown in Figure 1.

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Figure 1. Multiple Row Pairs

The preview window shows how the layout will look when realized on the layout canvas. In this example, it is clear that in order to make the design more compact, the larger transistors need to be folded.

Folding the transistors is very easy using the Symbolic Editor. Options on the toolbar allow the designer to fold the transistor by specifying either the number of segments desired or by specifying a width threshold. Once the option is set, all the layout engineer has to do is simply select the appropriate devices and have them folded such that the transistors fit neatly in the rows. Figure 2 shows how the design looks before and after folding.

 

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Figure 2. Before and After Folding

Analog designs are very sensitive to process variation, noise and other manufacturing variances. In order to mitigate the impact of these variances on critical pieces of circuitry, layout engineers use complex interdigitation patterns in addition to other layout techniques. This is a critical practice for analog design, because the effects of the variances, if not accounted for, can lead to a non-functioning piece of circuitry.

The Symbolic Editor provides a simple way to implement these complex patterns via the Pattern Generator. As well as being able to specify your own patterns, the Pattern Generator also includes a library of built-in patterns that can be used to interdigitate devices in a specific order. Take a differential pair, for example. The layout engineer can choose from a variety of different patterns as shown in Figure 3.

 

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Figure 3. Pattern Generator

The preview window makes it easy to see how the layout will look with the chosen pattern and, once the engineer is happy with the choice, s/he simply realizes the layout on the canvas. Figure 4 shows the results of choosing a Common Centroid pattern. With no constraints to enter, no code to write, layout is done in minutes vs. hours.

 

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Figure 4. Highlighted Devices as Part of a Common Centroid Pattern

Transistors are not the only devices that can take advantage of the Symbolic Editor. In the automotive world, it is often necessary to lay out banks of resistors. This is something the Symbolic Editor can also help with. Resistors can be chained serially in a variety of different routing patterns.

Using the Symbolic Editor allows the layout engineer to make simple graphical choices of how the layout needs to look and then have the detailed placement taken care of by the placement engine. It makes it easy to add or remove placement rows and columns, as well as insert dummy devices. Figure 6 shows the completed symbolic layout of two resistor banks with automatic insertion of dummies.

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Figure 6. Completed Symbolic Layout of Two Resistor Banks with Automatic Insertion of Dummies

Generating devices and placing them such that they meet all the design rules and produce a robust working design is about 30% of the time spent doing layout. Using a layout assistant like the Symbolic Editor really speeds this task up and makes the layout engineer much more productive. Synopsys has invested heavily in this technology over a period of 5+ years, such that we can address a broad range of design applications, unlike the recent offerings from other EDA vendors. Applicable to both FinFET and established planar CMOS nodes, the Symbolic Editor makes analog cell layout quick and easy.

To learn more about how the Symbolic Editor can help to rapidly create analog cells, check out Custom Compiler Webisode #6 that shows the Symbolic Editor in action.

Rapid Custom Digital Cell Layout with the Symbolic Editor

Thursday, November 3rd, 2016

In the ‘Custom Compiler Layout Assistants (Part 1)’ blog post, I profiled the use of the symbolic editor and how it makes placing devices that need to be in a specific interdigitated pattern (for example, a differential pair) very easy. With no constraints to enter and no code to write, layout is done in minutes vs. hours.

However, there is a lot more to the symbolic editor than the ability to simplify interdigitation. One good example is the ability to define multiple P and N row pairs and then symbolically chain and fold the transistors such that you get them to fit neatly in the rows. This is a key feature that allows you to not only control the aspect ratio of the design, but to very rapidly create a custom digital cell layout, as shown in Figure 1.

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Figure 1. Multiple Row Pairs

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Custom Compiler at DAC 2016

Monday, August 8th, 2016

DAC 2016 saw the first Synopsys custom design luncheon to feature Custom Compiler. It was a sold out event with 150 customer attendees eager to hear from Synopsys and other customers about how Synopsys is progressing in the custom design space. Antun Domic, Executive VP and General Manager of Synopsys’ Design Group moderated the event which included speakers from STMicroelectronics, GSI Technology, Samsung Foundry and the Synopsys IP team. For those of you who missed the live event, following is a short summary of the event highlights.

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Antun opened the proceedings and presented Synopsys’ fresh approach to custom layout with Custom Compiler. He shared details of the pioneering visually-assisted automation technologies that speed up custom design tasks, reduce iterations and enable reuse.

Antun then went on to introduce each of the customer speakers who related their experiences using Custom Compiler and how visually-assisted automation helped them reduce their layout efforts from days to hours.

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Custom Compiler In-Design Assistants (Part 2)

Thursday, July 14th, 2016

Planning which metal shape goes on which color (mask) is key when designing in a FinFET process, especially when propagating connections through the layout hierarchy. In addition, highly matched signals such as complementary clocks must be assigned to the same color, as routes on different masks have different resistances. So how do we ensure we are keeping things in order with respect to the matching of resistance and capacitance?

Custom Compiler’s In-Design assistants include a built-in engine that computes resistance of a net from a single source to a single destination or multiple destinations. It is an interactive tool that can be run often during the layout process, has a simple use model and a fast response time. To report the resistance of a net, the layout engineer simply selects the net of interest from either the layout, the design navigator or the schematic. The next step is to invoke the resistance report command which pops up in the electrical report menu. The report type is set to “Resistance” and the source and destination points are entered.  The report is run and the results are populated in the Electrical Reporter pane.
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Custom Compiler In-Design Assistants (Part 1)

Saturday, June 18th, 2016

On-line Design Rule Checking (DRC) is nothing new. The technology has been in use for years in a variety of different layout editors and yet nearly every layout engineer has a love/hate relationship with it. Why? Well it really comes down to the use model and the responsiveness of the application.

At the beginning of the design process, layout engineers love on-line DRC. But as the design progresses, the relationship begins to sour. The problem is that as the layout gets bigger and more complex, the performance invariably starts to fall off until it reaches a point where it becomes unacceptable and the layout engineer simply turns it off and resorts to running the occasional batch checks.

To really be effective, on-line DRC has to be an interactive tool that is run often during the layout process, so, as such it needs to have a simple use model and have a fast response. The engine needs to be ‘built-in’ to deliver the required performance and the feedback needs to be comprehensive enough to enable the layout engineer to quickly fix the violation.
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Custom Compiler Layout Assistants (Part 1)

Wednesday, June 1st, 2016

As mentioned previously, on March 30th Silicon Valley was buzzing with excitement. Synopsys revealed Custom Compiler, a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations and enable reuse at the SNUG Silicon Valley event. During this event, the R&D folks did a walkthrough of the technology ‘under-the-hood’ and showed the audience some cool layout assistants that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints. [Click here to view the videolog of the SNUG event.]

One of the layout assistants that was shown was the symbolic editor. This really is a must-have assistant when it comes to placing devices that need to be in a specific interdigitated pattern, like a differential pair. In the schematic, it is two symbols, but in the layout it could be hundreds of devices. The symbolic editor allows device placement to be edited in an easy and graphical manner and comes with a rich collection of predefined placement patterns. If you find a placement pattern you like, you can simply use it as-is and the symbolic editor will generate a correct-by-construction placement that you can instantiate in your layout. If you don’t find an exact match, you can easily use a pattern that is similar to what you need and rearrange the placement pattern graphically. No constraints to enter, no code to write and layout is done in minutes vs. hours.
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A Personal Invitation

Monday, May 23rd, 2016

I just wanted to take a moment to personally invite you to attend Synopsys’ Custom Compiler lunch event at DAC 2016 on Tuesday, June 7 in Austin, TX. At this event, engineers from GSI Technology, Samsung, STMicroelectronics, and Synopsys’ IP Group will showcase their experiences using the new Custom Compiler custom IC design tool with Visually-assisted Automation technologies.

As you’ll recall, Synopsys unveiled Custom Compiler on March 30 of this year at SNUG Silicon Valley. Custom Compiler is a new custom IC design solution that closes the FinFET productivity gap by cutting custom layout tasks from days to hours. It offers a fresh approach to custom design that employs Visually-assisted Automation technologies to speed up common design tasks, reduce iterations and enable reuse. Visually-assisted Automation technologies are a unique set of productivity aids that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints.
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Current Solutions for FinFET (Part 2)

Wednesday, April 6th, 2016

So, hopefully, you are now aware of Synopsys’ new Custom Compiler solution tuned for rapid implementation of FinFET custom designs. Custom Compiler features a pioneering visually-assisted automation flow that speeds up custom design tasks from days to hours, reduces iterations and enables reuse–very exciting stuff!

But I want to continue my previous discussion thread to help you get a better understanding of the scope of the challenges inherent in FinFET design (and hopefully avoid some pitfalls).

So, going back to where I left off earlier… PCells for custom layout have been a ‘no brainer’ for decades. They have done all the heavy lifting with respect to generating correct-by-construction layout and have been the most important ‘power’ tool for custom layout engineers. Now however, given the complexity of the FinFET process, they become absolutely vital.

Generating a FinFET device is easy when you have a PCell. When coded correctly, it will automatically generate the device such that the fins are properly spaced on the requisite ‘fin grid’ and that all the rules for Poly width/length, Diffusion width/length, Poly cuts and the like are adhered to. In addition to constructing the device design rule correctly, the PCell will also ensure that the metals in the device are colored correctly and abide by the color-related rules. As you can imagine, there is a lot of stuff going on in a FinFET PCell, but there is more. FinFET PCells have to be ‘smarter than the average PCell’ and they have to be in tune with the layout methodology.
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Breaking News: The Wait is Over!

Wednesday, March 30th, 2016

Over the last few blogs I have outlined some of the productivity challenges that the FinFET process brings with respect to custom layout. Today Synopsys unveiled Custom Compiler and ushered in a new era of visually-assisted automation. Custom Compiler has all the good stuff I’ve been saying is needed in earlier posts: a new custom design solution that closes the FinFET productivity gap by shortening custom design tasks from days to hours.

This is not a revamp of the old constraint-based legacy approach, it’s a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations and enable reuse.

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What’s visually-assisted automation, you may ask?

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