Tuesday, September 20th, 2016
In the blog ‘Custom Compiler In-Design Assistants (Part 2)’, I outlined how we can use StarRC to report capacitances on critical nets in the layout even when the design is still in flux and not completely LVS-clean. In addition to capacitance reports, we also showed resistance reporting which is critical for FinFET-based layouts. At advanced nodes, the impact of parasitics, electromigration (EM) and restricted design rules drive critical layout choices. Interconnect that does not meet resistance, or EM criteria and unbalanced capacitances on matched nets, can and often does adversely impact layout schedules. So the earlier in the layout phase the layout engineer can address these issues, the sooner he or she can close the design.
EM in particular is a notorious problem in the FinFET process due to the high drive of the transistors and thin metals. So let’s say, for example, the layout engineer has to route a critical net which could be susceptible to the impact of EM. This is a non-trivial task that could be quite challenging. However, if you use Custom Compiler, there are some very cool capabilities that make laying out interconnect that meets EM criteria very quick and very easy.
Sunday, August 28th, 2016
In past blogs I provided some insights into the differences between FinFET and planar CMOS designs and why layout engineers need to take these differences seriously.
In introducing Custom Compiler, Synopsys has taken a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations, and enable reuse. But sometimes, it’s not enough to simply say that a new tool is great–engineers need to see it to believe it.
As such, Synopsys has developed a collection of short technical webisodes
focusing on the unique features of Custom Compiler’s visually-assisted automation technologies that can shorten FinFET design tasks from days to hours.
The first webisode highlights how the symbolic editor enables layout engineers to create and optimize device placements at a high level of abstraction. We show how to rapidly create complex layout patterns for FinFET devices, as well as multi-row placements for PMOS and NMOS transistors, at a symbolic level without having to worry about design rules, connectivity or parameter values.
The second webisode highlights how Custom Compiler’s routing assistant enables layout engineers to route hundreds of connections with a simple click and drag of the mouse. We show how to rapidly route complex interdigitated layouts of FinFET devices, as well as simple multi-row placements for PMOS and NMOS transistors.
Monday, August 8th, 2016
DAC 2016 saw the first Synopsys custom design luncheon to feature Custom Compiler. It was a sold out event with 150 customer attendees eager to hear from Synopsys and other customers about how Synopsys is progressing in the custom design space. Antun Domic, Executive VP and General Manager of Synopsys’ Design Group moderated the event which included speakers from STMicroelectronics, GSI Technology, Samsung Foundry and the Synopsys IP team. For those of you who missed the live event, following is a short summary of the event highlights.
Antun opened the proceedings and presented Synopsys’ fresh approach to custom layout with Custom Compiler. He shared details of the pioneering visually-assisted automation technologies that speed up custom design tasks, reduce iterations and enable reuse.
Antun then went on to introduce each of the customer speakers who related their experiences using Custom Compiler and how visually-assisted automation helped them reduce their layout efforts from days to hours.
Saturday, June 18th, 2016
On-line Design Rule Checking (DRC) is nothing new. The technology has been in use for years in a variety of different layout editors and yet nearly every layout engineer has a love/hate relationship with it. Why? Well it really comes down to the use model and the responsiveness of the application.
At the beginning of the design process, layout engineers love on-line DRC. But as the design progresses, the relationship begins to sour. The problem is that as the layout gets bigger and more complex, the performance invariably starts to fall off until it reaches a point where it becomes unacceptable and the layout engineer simply turns it off and resorts to running the occasional batch checks.
To really be effective, on-line DRC has to be an interactive tool that is run often during the layout process, so, as such it needs to have a simple use model and have a fast response. The engine needs to be ‘built-in’ to deliver the required performance and the feedback needs to be comprehensive enough to enable the layout engineer to quickly fix the violation.
Wednesday, June 15th, 2016
To all of you who attended DAC last week in Austin, TX–welcome back! I hope you were among the 175+ people who attended the Custom Compiler lunch event on Tuesday, June 7 to hear directly from engineers at GSI Technology, Samsung, STMicroelectronics and Synopsys’ IP group who described how Custom Compiler’s visually-assisted automation improves their productivity for both FinFET and established-node designs. We’ll be posting a videolog of the presentations on the Synopsys web site soon for those who missed the live event.
In the last blog I detailed the Symbolic Editor Layout Assistant and showed how the layout engineer can make simple graphical choices of how the layout needs to look and then have the placement taken care of by a placement engine. In this post I will outline another layout assistant: the Routing Assistant. The routing task is one that absolutely screams out for an automated approach, however past efforts have required a great deal of text-based constraints to get anything near to what you really want.
Custom Compiler’s Routing Assistant is a perfect combination of user guidance and automation. It’s a visually-assisted approach that allows the layout engineer to simply click on the starting point of the route and then drag the cursor in the direction they want the routing to follow. As the cursor moves along, behind the scenes the routing engine searches for connections that it can make. When it finds a connection it automatically taps to the pin without the layout engineer having to enter a mouse click. The user simply guides the router with the mouse and it fills in the routing details automatically.
Wednesday, June 1st, 2016
As mentioned previously, on March 30th Silicon Valley was buzzing with excitement. Synopsys revealed Custom Compiler, a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations and enable reuse at the SNUG Silicon Valley event. During this event, the R&D folks did a walkthrough of the technology ‘under-the-hood’ and showed the audience some cool layout assistants that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints. [Click here to view the videolog of the SNUG event.]
One of the layout assistants that was shown was the symbolic editor. This really is a must-have assistant when it comes to placing devices that need to be in a specific interdigitated pattern, like a differential pair. In the schematic, it is two symbols, but in the layout it could be hundreds of devices. The symbolic editor allows device placement to be edited in an easy and graphical manner and comes with a rich collection of predefined placement patterns. If you find a placement pattern you like, you can simply use it as-is and the symbolic editor will generate a correct-by-construction placement that you can instantiate in your layout. If you don’t find an exact match, you can easily use a pattern that is similar to what you need and rearrange the placement pattern graphically. No constraints to enter, no code to write and layout is done in minutes vs. hours.
Monday, May 23rd, 2016
I just wanted to take a moment to personally invite you to attend Synopsys’ Custom Compiler lunch event at DAC 2016 on Tuesday, June 7 in Austin, TX. At this event, engineers from GSI Technology, Samsung, STMicroelectronics, and Synopsys’ IP Group will showcase their experiences using the new Custom Compiler custom IC design tool with Visually-assisted Automation technologies.
As you’ll recall, Synopsys unveiled Custom Compiler on March 30 of this year at SNUG Silicon Valley. Custom Compiler is a new custom IC design solution that closes the FinFET productivity gap by cutting custom layout tasks from days to hours. It offers a fresh approach to custom design that employs Visually-assisted Automation technologies to speed up common design tasks, reduce iterations and enable reuse. Visually-assisted Automation technologies are a unique set of productivity aids that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints.
Tuesday, May 17th, 2016
In the last blog I outlined the kind of tool that layout engineers need in order to get a good placement that delivers robust working silicon within the confines of the FinFET process. We concluded that a guided/interactive approach that is fast and easy to refine such that you do get the result you want is the way to go.
So where else can we look for more efficiency during layout? Well, once you have placed your devices, the next step is to route up all the connections that cannot be completed by simple abutment. Again, because you could be dealing with hundreds of devices [remember the differential pair example? See the “Current Solutions for FinFET (Part 1)” blog] the routing task is one that absolutely screams out for an automatic approach, and there have been lots of efforts at automating custom routing in the past.
Tuesday, May 10th, 2016
Over the last series of blogs we have looked at which tools the layout engineer has available to him/her to help deal with the complexity of doing layout with FinFETs. Even though there are tools that help, the fact is there is still a productivity hit when comparing the time it takes to do a FinFET-based layout vs. a planar CMOS layout. When I asked my layout colleagues “How much longer does it take to do a FinFET-based design vs. planar CMOS?”, they said it takes 2-3X longer.
So, if we are to recoup layout productivity when doing a FinFET-based design, which areas should we focus on? Well, let’s start at the very beginning, which, according to Julie Andrews in The Sound of Music, is a very good place to start. The task of generating the devices and placing them such that they meet all the design rules and will produce a robust working design is about 30% of the layout time. So if we can speed up this task then we will gain back some of the productivity we lost due to the complexity of the FinFET process.