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Graham Etchells, Director of Product Marketing at Synopsys
Graham Etchells, Director of Product Marketing at Synopsys
Graham Etchells started in EDA before it was termed EDA. He has held marketing and sales positions at several companies and has been chasing the holy grail of analog/custom layout automation ever since he was a marketing director at Cadence in the mid-1990s. He says past experience indicates we may … More »

Seeing is Believing

August 28th, 2016 by Graham Etchells, Director of Product Marketing at Synopsys

In past blogs I provided some insights into the differences between FinFET and planar CMOS designs and why layout engineers need to take these differences seriously.

In introducing Custom Compiler, Synopsys has taken a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations, and enable reuse. But sometimes, it’s not enough to simply say that a new tool is great–engineers need to see it to believe it.

As such, Synopsys has developed a collection of short technical webisodes focusing on the unique features of Custom Compiler’s visually-assisted automation technologies that can shorten FinFET design tasks from days to hours.
The first webisode highlights how the symbolic editor enables layout engineers to create and optimize device placements at a high level of abstraction. We show how to rapidly create complex layout patterns for FinFET devices, as well as multi-row placements for PMOS and NMOS transistors, at a symbolic level without having to worry about design rules, connectivity or parameter values.
The second webisode highlights how Custom Compiler’s routing assistant enables layout engineers to route hundreds of connections with a simple click and drag of the mouse. We show how to rapidly route complex interdigitated layouts of FinFET devices, as well as simple multi-row placements for PMOS and NMOS transistors.

Webisodes 3 highlights how Custom Compiler’s In-Design assistant for DRC enables layout engineers to easily check their layout for design rule correctness with a simple click of the mouse. We show how to selectively check portions of the design and how to set up select categories of checks and save them for future use. In addition, we show how to highlight violations and query the error types.
Webisode 4 highlights how Custom Compiler’s In-Design Assistants for resistance, capacitance, and electromigration checking enable layout engineers to easily verify whether their layout is meeting electrical specifications with a simple click of the mouse. We show how to selectively check critical nets in the design and report on their resistance, capacitance, and EM violations directly from the layout, without the need for an LVS-clean design.
I encourage you to watch these webisodes to see for yourself how easy it can be to successfully lay out a FinFET design using Custom Compiler. And for even more information, you can always visit

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