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Archive for July 14th, 2016

Custom Compiler In-Design Assistants (Part 2)

Thursday, July 14th, 2016

Planning which metal shape goes on which color (mask) is key when designing in a FinFET process, especially when propagating connections through the layout hierarchy. In addition, highly matched signals such as complementary clocks must be assigned to the same color, as routes on different masks have different resistances. So how do we ensure we are keeping things in order with respect to the matching of resistance and capacitance?

Custom Compiler’s In-Design assistants include a built-in engine that computes resistance of a net from a single source to a single destination or multiple destinations. It is an interactive tool that can be run often during the layout process, has a simple use model and a fast response time. To report the resistance of a net, the layout engineer simply selects the net of interest from either the layout, the design navigator or the schematic. The next step is to invoke the resistance report command which pops up in the electrical report menu. The report type is set to “Resistance” and the source and destination points are entered.  The report is run and the results are populated in the Electrical Reporter pane.

S2C: FPGA Base prototyping- Download white paper

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