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Graham Etchells, Director of Product Marketing at Synopsys
Graham Etchells, Director of Product Marketing at Synopsys
Graham Etchells started in EDA before it was termed EDA. He has held marketing and sales positions at several companies and has been chasing the holy grail of analog/custom layout automation ever since he was a marketing director at Cadence in the mid-1990s. He says past experience indicates we may … More »

What’s Really Needed for FinFET Layout (Part 1)

May 10th, 2016 by Graham Etchells, Director of Product Marketing at Synopsys

Over the last series of blogs we have looked at which tools the layout engineer has available to him/her to help deal with the complexity of doing layout with FinFETs. Even though there are tools that help, the fact is there is still a productivity hit when comparing the time it takes to do a FinFET-based layout vs. a planar CMOS layout. When I asked my layout colleagues “How much longer does it take to do a FinFET-based design vs. planar CMOS?”, they said it takes 2-3X longer.

So, if we are to recoup layout productivity when doing a FinFET-based design, which areas should we focus on? Well, let’s start at the very beginning, which, according to Julie Andrews in The Sound of Music, is a very good place to start. The task of generating the devices and placing them such that they meet all the design rules and will produce a robust working design is about 30% of the layout time. So if we can speed up this task then we will gain back some of the productivity we lost due to the complexity of the FinFET process.

Because one device in the schematic can translate to hundreds of devices in the layout, layout engineers need a fast yet simple way to generate the device and get the individual transistors grouped together such that the device will work properly and adheres to the strict layout-dependent rules that the FinFET process requires. Take a differential pair, for example. In the schematic it is two symbols, but in the layout it could be hundreds of devices. To ensure good analog layout that will work, it is typical for these devices to be interdigitated in a specific pattern. Doing this by hand is time-consuming, tedious, and error-prone. This is where you need some automation. Not the ‘push the button and see what I get’ kind of automation, but a guided/interactive approach that is fast and easy to refine such that you get the result you want. This approach is especially important when implementing ECO changes.

Having the layout engineer make simple graphical choices of how the layout needs to look and then having the placement taken care of by the placement engine is the fastest way to achieving correct layout. Using this user-guided interactive approach cuts the layout time from hours to minutes.

In the next post, we’ll examine where else we can we look to gain back some layout productivity…

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One Response to “What’s Really Needed for FinFET Layout (Part 1)”

  1. Arulnath says:

    This is one of the best article read in recent times. continue your good work.

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