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 Custom Layout Insights

Archive for May, 2016

A Personal Invitation

Monday, May 23rd, 2016

I just wanted to take a moment to personally invite you to attend Synopsys’ Custom Compiler lunch event at DAC 2016 on Tuesday, June 7 in Austin, TX. At this event, engineers from GSI Technology, Samsung, STMicroelectronics, and Synopsys’ IP Group will showcase their experiences using the new Custom Compiler custom IC design tool with Visually-assisted Automation technologies.

As you’ll recall, Synopsys unveiled Custom Compiler on March 30 of this year at SNUG Silicon Valley. Custom Compiler is a new custom IC design solution that closes the FinFET productivity gap by cutting custom layout tasks from days to hours. It offers a fresh approach to custom design that employs Visually-assisted Automation technologies to speed up common design tasks, reduce iterations and enable reuse. Visually-assisted Automation technologies are a unique set of productivity aids that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints.

What’s Really Needed for FinFET Layout (Part 2)

Tuesday, May 17th, 2016

In the last blog I outlined the kind of tool that layout engineers need in order to get a good placement that delivers robust working silicon within the confines of the FinFET process. We concluded that a guided/interactive approach that is fast and easy to refine such that you do get the result you want is the way to go.

So where else can we look for more efficiency during layout? Well, once you have placed your devices, the next step is to route up all the connections that cannot be completed by simple abutment. Again, because you could be dealing with hundreds of devices [remember the differential pair example? See the “Current Solutions for FinFET (Part 1)” blog] the routing task is one that absolutely screams out for an automatic approach, and there have been lots of efforts at automating custom routing in the past.

What’s Really Needed for FinFET Layout (Part 1)

Tuesday, May 10th, 2016

Over the last series of blogs we have looked at which tools the layout engineer has available to him/her to help deal with the complexity of doing layout with FinFETs. Even though there are tools that help, the fact is there is still a productivity hit when comparing the time it takes to do a FinFET-based layout vs. a planar CMOS layout. When I asked my layout colleagues “How much longer does it take to do a FinFET-based design vs. planar CMOS?”, they said it takes 2-3X longer.

So, if we are to recoup layout productivity when doing a FinFET-based design, which areas should we focus on? Well, let’s start at the very beginning, which, according to Julie Andrews in The Sound of Music, is a very good place to start. The task of generating the devices and placing them such that they meet all the design rules and will produce a robust working design is about 30% of the layout time. So if we can speed up this task then we will gain back some of the productivity we lost due to the complexity of the FinFET process.

S2C: FPGA Base prototyping- Download white paper

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