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Graham Etchells, Director of Product Marketing at Synopsys
Graham Etchells, Director of Product Marketing at Synopsys
Graham Etchells started in EDA before it was termed EDA. He has held marketing and sales positions at several companies and has been chasing the holy grail of analog/custom layout automation ever since he was a marketing director at Cadence in the mid-1990s. He says past experience indicates we may … More »

Current Solutions for FinFET (Part 2)

 
April 6th, 2016 by Graham Etchells, Director of Product Marketing at Synopsys

So, hopefully, you are now aware of Synopsys’ new Custom Compiler solution tuned for rapid implementation of FinFET custom designs. Custom Compiler features a pioneering visually-assisted automation flow that speeds up custom design tasks from days to hours, reduces iterations and enables reuse–very exciting stuff!

But I want to continue my previous discussion thread to help you get a better understanding of the scope of the challenges inherent in FinFET design (and hopefully avoid some pitfalls).

So, going back to where I left off earlier… PCells for custom layout have been a ‘no brainer’ for decades. They have done all the heavy lifting with respect to generating correct-by-construction layout and have been the most important ‘power’ tool for custom layout engineers. Now however, given the complexity of the FinFET process, they become absolutely vital.

Generating a FinFET device is easy when you have a PCell. When coded correctly, it will automatically generate the device such that the fins are properly spaced on the requisite ‘fin grid’ and that all the rules for Poly width/length, Diffusion width/length, Poly cuts and the like are adhered to. In addition to constructing the device design rule correctly, the PCell will also ensure that the metals in the device are colored correctly and abide by the color-related rules. As you can imagine, there is a lot of stuff going on in a FinFET PCell, but there is more. FinFET PCells have to be ‘smarter than the average PCell’ and they have to be in tune with the layout methodology.

So what’s so different about the layout methodology for FinFET? Well first and foremost, the layout methodology for FinFET is geared around ensuring that the design is routable. There is no point in having a correct-by-construction device if when you place it, it can’t be routed to. Remember my earlier post ‘Hurricane FinFET (Part 3)’ when I was talking about the fact that although the pitch for the base layers has shrunk considerably the metal pitch has not shrunk as much? Well that’s been done deliberately to make sure that there is sufficient space to make the design routable.

Routability is paramount such that it becomes the first rule of placement. So how do we go about placing a device such that it is routable and also meets the rules for ‘fin grid’ spacing? Well it’s simply a matter of ‘metal grids’, ‘fin grids’ and ‘smart’ FinFET PCells.

The ‘fin grids’ are defined in the process technology file which is delivered as part of the Interoperable Process Design Kit (iPDK) from the foundry. The ‘metal grids’ are defined by the layout methodology and the type of design you are doing, e.g., memory, SerDes, DDR, etc… When you open up your layout editor and point to a specific iPDK, the tool automatically generates the requisite ’metal grids’ and ‘fin grid’. These grids can be displayed and the display can be toggled on and off. So now you have a visual aid as to where to place your FinFET PCell. However, the last thing you want to be doing is zooming in and out to see where to place your device. That’s where the ‘smart’ FinFET PCell comes in.

The PCell is coded such that when the device is placed, the layout tool snaps the metal contact in the device to the nearest appropriate ‘metal grid’. This ensures that you can connect to the cell on that metal layer and you don’t need to zoom in to get a correct placement. Although we now have a device that we can route to, we don’t necessarily have a manufacturable design. You see, the PCells are coded in isolation and have no knowledge of the spacing between ‘metal grids’ and ‘fin grid’ in the layout. That’s because the grid is not always a uniform grid. This means that you can end up with the fins in the device not aligning with the ‘fin grid’. To overcome this, a ‘call-back’ is triggered to snap the diffusion to the ‘fin grid’ so that the design is both DRC clean and routable.

So, let’s recap. We can use schematic PCells to deal with the mapping of one schematic device to potentially hundreds of physical devices and make parameter changes easy to incorporate. We can use ‘smart’ FinFET PCells to ensure we have a routable and manufacturable design. But what do we have to help us with electromigration and density checks? I’ll address that in my next post.

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