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Graham Etchells, Director of Product Marketing at Synopsys
Graham Etchells, Director of Product Marketing at Synopsys
Graham Etchells started in EDA before it was termed EDA. He has held marketing and sales positions at several companies and has been chasing the holy grail of analog/custom layout automation ever since he was a marketing director at Cadence in the mid-1990s. He says past experience indicates we may … More »

Hurricane FinFET (Part 2)

 
March 9th, 2016 by Graham Etchells, Director of Product Marketing at Synopsys

So, FinFETs rule! They give the designer so much flexibility in trading off power and performance that it should be a no-brainer to adopt the technology–right?

Well, every silver lining has to have a cloud, and in the case of FinFETs there are quite a few.

I polled a number of layout designers who have first-hand experience of laying out FinFET designs and asked them “What’s the impact of FinFET?”. Here’s what they told me requires them to do extra work:

  • First off is the sheer number of rules that they have to be conscious of. The number of rules has more than doubled compared to a 40-nm process. Of special concern are some of the density rules that now have to be applied to a lot more layers.
  • Another area you have to pay particular attention to is maximum diffusion space. This forces devices to have guardrings around them so that you do not have too large a diffusion space. The diffusion in the guardring essentially breaks the space check. So you either have to have devices very close together or spaced by guardrings.
  • Process restrictions require that every fin has to have an equal height. In addition there are strict limitations on the sizes of “W” and “L” that can be used. As a result a device that requires a large “W” (width) has to be quantized into multiple fin units that utilize the acceptable “W” and “L”.
    What this means in practice is that an innocent-looking single device in the schematic can be 100 devices in the physical layout! Add to that the fact that fins have to snap to specific grids and you have a massive layout challenge for even a simple circuit.

  • Double-patterning (DP) is required for all FinFET designs and as such the challenge of mask alignment comes into play. Catering for mask alignment requires a change in layout methodology. Mismatches between devices are unacceptable, especially for analog circuits where transistor matching and layout symmetry are vital to ensure correct circuit behavior.

So as you can see, there is lot more that needs to be considered when doing FinFET layout.

And you should see what you have to do for routing!!

But that’s another post…

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