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Archive for March, 2016

Breaking News: The Wait is Over!

Wednesday, March 30th, 2016

Over the last few blogs I have outlined some of the productivity challenges that the FinFET process brings with respect to custom layout. Today Synopsys unveiled Custom Compiler and ushered in a new era of visually-assisted automation. Custom Compiler has all the good stuff I’ve been saying is needed in earlier posts: a new custom design solution that closes the FinFET productivity gap by shortening custom design tasks from days to hours.

This is not a revamp of the old constraint-based legacy approach, it’s a fresh approach to custom design that employs visually-assisted automation technologies to speed up common design tasks, reduce iterations and enable reuse.

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What’s visually-assisted automation, you may ask?

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Current Solutions for FinFET (Part 1)

Monday, March 28th, 2016

What tools do we have in our FinFET toolbox that can help layout engineers manage the complexity that FinFETs inherently bring?

Well for my money, the best and most powerful tool we have to tackle FinFET complexity is the good old parameterized cell or PCell. PCells are not new, they have been around since the CALMA GDS days and along with Schematic-Driven Layout, have been instrumental in boosting layout productivity, as I have mentioned in my previous posts. PCells have typically been used to generate physical layout of pretty much all the devices needed for custom layout, from resistors to inductors, capacitors and, of course, the transistor. That is still the case for FinFET designs; however the role of the PCell has now been expanded to include the schematic PCell.

So what’s the big deal about a schematic PCell, you might ask? And why didn’t we have them before?

Well, some companies did use schematic PCells, but mainly to generate symbols. With FinFET there are many more reasons that a schematic PCell should be used. It boils down to three things: complexity, aesthetics, and productivity.

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Hurricane FinFET (Part 3)

Friday, March 18th, 2016

Continuing on the theme of FinFET layout, let’s consider what you have to do for routing. Again drawing on the experience of my layout colleagues who are still ‘in the business’ and dealing with FinFETs, here are a few landmines you will have to deal with.

One particular issue they encounter is that although the base layers have shrunk considerably, the shrink of the routing layers has not kept pace. Each new node has brought us smaller transistors, but the minimum metal pitch has not really changed. This really impacts layout floorplanning because designs that were once dictated by device area are now dictated by the ability to route the required signals. Double-/triple-patterning compounds the issue even further.
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Hurricane FinFET (Part 2)

Wednesday, March 9th, 2016

So, FinFETs rule! They give the designer so much flexibility in trading off power and performance that it should be a no-brainer to adopt the technology–right?

Well, every silver lining has to have a cloud, and in the case of FinFETs there are quite a few.

I polled a number of layout designers who have first-hand experience of laying out FinFET designs and asked them “What’s the impact of FinFET?”. Here’s what they told me requires them to do extra work:

  • First off is the sheer number of rules that they have to be conscious of. The number of rules has more than doubled compared to a 40-nm process. Of special concern are some of the density rules that now have to be applied to a lot more layers.
  • Another area you have to pay particular attention to is maximum diffusion space. This forces devices to have guardrings around them so that you do not have too large a diffusion space. The diffusion in the guardring essentially breaks the space check. So you either have to have devices very close together or spaced by guardrings.
  • Process restrictions require that every fin has to have an equal height. In addition there are strict limitations on the sizes of “W” and “L” that can be used. As a result a device that requires a large “W” (width) has to be quantized into multiple fin units that utilize the acceptable “W” and “L”.
    What this means in practice is that an innocent-looking single device in the schematic can be 100 devices in the physical layout! Add to that the fact that fins have to snap to specific grids and you have a massive layout challenge for even a simple circuit.

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