Archive for the ‘Uncategorized’ Category
Thursday, June 18th, 2015
Last week I attended the Design Automation Conference as an intrepid reporter to put my ear to the ground and take note of what is happening in the industry. I wrote some daily review blogs of my time on the show floor (which can be seen here, Day 1, Day 2, Day 3) but I have come up with some talking points from the conference. These are the topics that I found got most air time both in the booths and in the many speeches, presentations and panel discussions across the week. Let me know what you think about them in the comments section below.
On Tuesday morning the VP of Foundries gave an insightful presentation on their advancements over the past 12 months and their vision for the foreseeable future. His words carry an extra amount of weight when you consider that in 2014 he promised 14nm silicon in a year’s time and was able to deliver on his word. It was not done in a silo however, and the phrase he used of “relentless collaboration” between EDA, IP companies and foundries is absolutely crucial to marching on with the progress he outlined, of seeing silicon for 10nm in 2016. The other key point he made was that each foundry process must be aligned to and optimized for the target segment. For example reducing the process node for server density and mobile, but there is still plenty of innovation at higher nodes for automotive, wearable and of course IoT. The same breakfast session showed proof of what can happen when partners collaborate. ARM®, and Samsung managed to implement a quad-core Cortex®-A53 processor design with CoreLink™ CCN-502 designed for networking on a 14nm LPP process in a timescale of just four weeks.
Wednesday, June 3rd, 2015
The modern SoC is designed with many modular IP blocks that have been commercially licensed or reused from previous designs, along with some new proprietary components. Integrating all of the components has typically proven to be time-consuming and error-prone as designers stitch their SoCs together by hand or rigid and outdated scripts. Challenges also exist in the form of highly configurable IP blocks such as the interconnect fabric and debug & trace subsystem.
To address these issues ARM® launched three new tools today as part of an IP Tooling suite. They have been designed to solve challenges associated with SoC configurability and integration while reducing time to market with at least an 8x improvement in schedule.
Tuesday, May 26th, 2015
Some innovations give such an exponential productivity shift that they are often only appreciated when viewed with the perspective of history. Isambard Kingdom Brunel built the first train line from London to Bristol and cut down the travel times from days to hours. In doing so he actually moved time itself; at the time Bristol was 30 minutes behind London. Clocks in the 19th century were based off sunrise and sunset in each location as it was never necessary to be so precise when travel between two places meant a much longer journey. However the real benefit he provided was literally giving time to people, by shortening the travel time it enabled people to dedicate time to solving other problems. The spread of train tracks across the UK and the rest of the world enabled the rapid development of the Industrial Revolution that provided the foundation for the modern world. There is a fantastic documentary on Isambard Brunel on YouTube for those who wish to find out more.
The Clifton suspension bridge in Bristol. A revolutionary construct in 1864 that dramatically cut travel times between London and Bristol
Monday, May 18th, 2015
Ladies and gentlemen it’s that time of the year again, DAC is less than three weeks away! I will be in San Francisco to provide daily updates of all the major news from the Moscone Center for those of you who won’t be attending, so you won’t miss out on anything from the three day exhibition. The ARM Connected Community is the place to be to find out about DAC news, photos, videos, partner announcements and gossip from the show floor throughout the event! In this blog I’ll give you a flavour of what DAC is all about as well as highlighting how ARM is engaging with partners in workshops, panels and poster sessions. Here is a link to the full list of ARM presentations and panels at DAC.
Monday, April 13th, 2015
System coherency remains an important factor for SoC design starts. The ARM® CoreLink™ CCI-400 has seen great success, over 35 licensees across multiple applications from mobile big.LITTLE, to network infrastructure, digital TV and automotive infotainment. In all these applications there is a need for full coherency for multiple processor clusters, and IO coherency for accelerators and interfaces such as networking and PCIe.
Compared to CoreLink CCI-400, the recently-announced CoreLink CCI-500 offers up to double the peak system bandwidth, a 30 percent processor memory performance increase, reduced system power, and high scalability and configurability to suit the needs of diverse applications. This blog will go into more detail on these benefits, but first I’ll give a quick recap of cache coherency and shared data.
Tuesday, April 7th, 2015
This is the second part of a series of blogs about hardware coherency. In the first blog I introduced the fundamentals of cache coherency: Extended System Coherency – Part 1 – Cache Coherency Fundamentals
This part talks about the implementation of hardware cache coherency and use cases.
Implementing Hardware Coherency
ARM’s first implementations of AMBA® 4 ACE include the ARM® CoreLink™ CCI-400 Cache Coherent Interconnect, ARM Cortex®-A15 and Cortex-A7 processors. These products were first released to our silicon partners in 2011, and we’ve seen the first big.LITTLE™ products come to market in 2013.
Monday, March 23rd, 2015
The EDA industry is all about finding innovative ways of improving performance and in many ways hardware system coherency is an important part of connecting the intelligence of an SoC. It is widely known that SoCs and their component IP blocks are ever more complicated, and I am interested in easing this through extending coherency across the system. This blog is the first in a series and starts with cache coherency fundamentals.
Tuesday, March 10th, 2015
Hello all I’m Neil Parris, a senior product manager at ARM. I’ll be blogging from time to time about certain issues surrounding EDA and IP integration in particular. I hope to provide some valuable insight into the sometimes murky world of SoC development. Please enjoy the content and don’t hesitate to leave comments or ask questions. My blogging debut on this platform comes in the form of an interview, as I sat down and chatted to David Murray. If you don’t know him, David joined ARM last year as part of the Duolog acquisition and is working as an IP Tooling Architect. He is incredibly enthusiastic and articulate so it is always a pleasure to speak with him.