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Archive for June, 2015

7 things I learned at 52DAC

Thursday, June 18th, 2015

Last week I attended the Design Automation Conference as an intrepid reporter to put my ear to the ground and take note of what is happening in the industry. I wrote some daily review blogs of my time on the show floor (which can be seen here, Day 1, Day 2, Day 3) but I have come up with some talking points from the conference. These are the topics that I found got most air time both in the booths and in the many speeches, presentations and panel discussions across the week. Let me know what you think about them in the comments section below.

Relentless collaboration

On Tuesday morning the VP of Samsung Electronics Foundries gave an insightful presentation on their advancements over the past 12 months and their vision for the foreseeable future. His words carry an extra amount of weight when you consider that in 2014 he promised 14nm silicon in a year’s time and was able to deliver on his word. It was not done in a silo however, and the phrase he used of “relentless collaboration” between EDA, IP companies and foundries is absolutely crucial to marching on with the progress he outlined, of seeing silicon for 10nm in 2016. The other key point he made was that each foundry process must be aligned to and optimized for the target segment. For example reducing the process node for server density and mobile, but there is still plenty of innovation at higher nodes for automotive, wearable and of course IoT. The same breakfast session showed proof of what can happen when partners collaborate. ARM®, Synopsys and Samsung managed to implement a quad-core Cortex®-A53 processor design with CoreLink™ CCN-502 designed for networking on a 14nm LPP process in a timescale of just four weeks.

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System Assembly through Intelligent Configuration

Wednesday, June 3rd, 2015

 

The modern SoC is designed with many modular IP blocks that have been commercially licensed or reused from previous designs, along with some new proprietary components. Integrating all of the components has typically proven to be time-consuming and error-prone as designers stitch their SoCs together by hand or rigid and outdated scripts. Challenges also exist in the form of highly configurable IP blocks such as the interconnect fabric and debug & trace subsystem.

To address these issues ARM® launched three new tools today as part of an IP Tooling suite. They have been designed to solve challenges associated with SoC configurability and integration while reducing time to market with at least an 8x improvement in schedule.

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