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Archive for June 11th, 2009

FEL: Improving collaborative hardware development experience

Thursday, June 11th, 2009

One of the many faces of digital hardware design entails tracking many files to be fed to multiple EDA tools. The eventual reports or netlists are carefully analysed and logged as part of the sign-off methodology. Each company tracks these project dependent files under a certain directory structure and under a certain revision controlled system of their choice.

The development cycle Fedora Electronic Lab 12 has started. One key feature for the next Fedora 12 release will be improving “collaborative hardware development experience” on Fedora. As a test-case scenario, let’s imagine 4 persons (from 4 different continents) have encountered each other using a particular social networking medium and want to engage into the development of a FPGA project.

While Fedora Electronic Lab already includes the respective simulators for digital design (VHDL/Verilog), waveforms viewers, schematic editors, PCB layout editor and Fedora’s different webserver and security solutions, these 4 persons (test-case scenario) should not have any issue with the latest Fedora 11 release.


DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL

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