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Ankit Gopani
Ankit Gopani
Ankit Gopani is Experienced Design Verification Engineer. He has been working in the field of ASIC Design and verification and have worked on various IP, SOC, module and subsystem level verification. Ankit has been in the industry for more than 12 years. He is well-known name in the field of ASIC … More »

System Verilog : Which final is Final ?

March 14th, 2013 by Ankit Gopani

Dear Reader,

Recently I posted one blog post “System Verilog Final Means Final !”

As we all know final means final in system Verilog, Final block will get called at the end of the simulation before $finish. Now with this understanding we can have few questions. Recently few engineers have asked me some questions and thought answering those questions. Questions asked are listed below

  1. Is multiple final block is allowed in System Verilog?
  2. If yes, what will be the execution order in simulation, which final is final?

Here are the answers to this questions :

Multiple final blocks are allowed in system Verilog, you can define multiple final block in your testbench. Some time you might require to use final blocks in different places of environment. Here we need to understand one most important thing on final block is that, final blocks are called at the end of the simulation before $finish. It is like a calling a function which executes in zero simulation time.

If you have multiple final block in your testbench all final blocks are called at same simulation time before your simulation ends. Let’s take an example to have better understanding:

program ankit_with_ankit;

class final_test;

   task final_activity();
      $display (“ASIC With Ankit 1 @%t”,$time);
     $display (“ASIC With Ankit 2 @%t”,$time);


initial begin

    final_test ft;
    ft = new;

final begin
   $display (“ASIC With Ankit 3 @%t”,$time);

final begin
   $display (“ASIC With Ankit 4 @%t”,$time);


Simulation Result:

ASIC With Ankit 1 @ 0
ASIC With Ankit 2 @ 10
ASIC With Ankit 3 @ 10
ASIC With Ankit 4 @ 10

Here you can observe that I have used 2 final blocks in this simple exercises. You can have less or more based on your testbench requirement. When you run this with any simulator result will tell you all the final blocks will be called at same simulation time. So you could see all the messages for final blocks will be print at same simulation time. This is the reason you could see printing time for all the messages defined in the final blocks are 10ns.

So answer to question ‘which final is final?’ is ‘All finals are final’!

I hope this will give you a more understanding on final block usage and execution. Comments, suggestions are welcome.

Happy Reading!

ASIC With Ankit

Category: ASIC FPGA Verification

2 Responses to “System Verilog : Which final is Final ?”

  1. Narendra says:

    Hi Ankit,
    Thanks for the example…

    Assuming there is no $finish statement , the Final bloack should be triggered at the End of initial block , where the $time will be at10ns…

    shouldn’t that make the Last two Display statements at time of 10ns ?
    ASIC With Ankit 1 @ 0
    ASIC With Ankit 2 @ 10
    ASIC With Ankit 3 @ 10
    ASIC With Ankit 4 @ 10

    correct me if am wrong..!!

    • Ankit Gopani says:

      Hi Narendra,

      Your underataing is now correct ! There was a typo in simulation result.
      I have updated the post, last two display statement will get print at time of 10ns.

      Happy reading and keep sharing the knowledge!

      Ankit (ASIC WIth Ankit)

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