ASIC with Ankit
Ankit Gopani is Lead Design Verification Engineer at SmartPlay Inc, USA. Ankit has been in the industry for more than 9 years. He pursued Diploma in E.C, B.E in Electronics and Communication and MBA in software project management.
System Verilog : Which final is Final ?
March 14th, 2013 by Ankit Gopani
Recently I posted one blog post “System Verilog Final Means Final !”
As we all know final means final in system Verilog, Final block will get called at the end of the simulation before $finish. Now with this understanding we can have few questions. Recently few engineers have asked me some questions and thought answering those questions. Questions asked are listed below
Here are the answers to this questions :
Multiple final blocks are allowed in system Verilog, you can define multiple final block in your testbench. Some time you might require to use final blocks in different places of environment. Here we need to understand one most important thing on final block is that, final blocks are called at the end of the simulation before $finish. It is like a calling a function which executes in zero simulation time.
If you have multiple final block in your testbench all final blocks are called at same simulation time before your simulation ends. Let’s take an example to have better understanding:
ASIC With Ankit 1 @ 0
Here you can observe that I have used 2 final blocks in this simple exercises. You can have less or more based on your testbench requirement. When you run this with any simulator result will tell you all the final blocks will be called at same simulation time. So you could see all the messages for final blocks will be print at same simulation time. This is the reason you could see printing time for all the messages defined in the final blocks are 10ns.
So answer to question ‘which final is final?’ is ‘All finals are final’!
I hope this will give you a more understanding on final block usage and execution. Comments, suggestions are welcome.
Category: ASIC FPGA Verification
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