ASIC with Ankit
Ankit Gopani is Lead Design Verification Engineer at SmartPlay Inc, USA. Ankit has been in the industry for more than 9 years. He pursued Diploma in E.C, B.E in Electronics and Communication and MBA in software project management.
System Verilog: final means final !
February 23rd, 2013 by Ankit Gopani
Today I would like to share some basic things on ‘final’block in System Verilog. This is a newly added feature in System Verilog over Verilog. Final block is good for summery information. You can have summery information printed in log file at the end of simulation.
Final block executes at the end of the simulations without delays. ‘final’ block is like an initial block in SV only difference is that it occurs at the end of the simulations. Final block does not allow delays and time consuming or blocking activities and because of this reason it typically used in display statistical information on simulation result. Final block executes in zero time. Considering this nature of execution it is similar to ‘function’.Function also executes in zero time and does not allow timing related or blocking type of activities.
int error, warning;
//Main program activities…..
$display (“Test is done with %d errors and %d warnings”, error, warning);
Simulation ends means what?
Simulation ends when last initial block ends in theprogram. When last initial block ends, it implicitly calls $exit which tells particular program is done! When every program is completed (exited) an implicit call to $finish is done. User can call $finish any time whenever he/she wants to end the simulation.
This process does not mean that your simulation is over, a module or program can have one or more ‘final’blocks that contains code to be run just before simulator terminates/finishes.
This is a great place to perform certain activity in your simulation like:
- Cleaning up tasks such as closing files
- Printing reports which can have summary of number of warnings, errors etc..
- Display statistic information about the simulation
Final block can only trigger once in a simulations and because that I name it as ‘final means final’, you cannot call it again!
Category: ASIC FPGA Verification