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Archive for February 23rd, 2013

System Verilog: final means final !

Saturday, February 23rd, 2013

Dear Readers,

Today I would like to share some basic things on finalblock in System Verilog. This is a newly added feature in System Verilog over Verilog. Final block is good for summery information. You can have summery information printed in log file at the end of simulation.

Final block executes at the end of the simulations without delays. final block is like an initial block in SV only difference is that it occurs at the end of the simulations. Final block does not allow delays and time consuming or blocking activities and because of this reason it typically used in display statistical information on simulation result. Final block executes in zero time. Considering this nature of execution it is similar to function.Function also executes in zero time and does not allow timing related or blocking type of activities.

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