ASIC with Ankit
Ankit Gopani is Lead Design Verification Engineer at SmartPlay Inc, USA. Ankit has been in the industry for more than 9 years. He pursued Diploma in E.C, B.E in Electronics and Communication and MBA in software project management.
Designs or Verification Test bench becomes complex and difficult to handle at end of the day!!
February 4th, 2013 by Ankit Gopani
As we all know debugging is not an easy task and requires lots of attentions and effort to figure out the issues! Well, it is not at free of cost! (Debugging is not free!) This is true for both Design as well as Verification engineers.
ASIC/FPGAs are becoming more and more complex day by day and because of that RTL design and Verification environments are becoming super complex! Usually engineers start writing a code with good understanding in mind from defined specification or standards. With the complexity and sometime way of writing code makes design code / verification environment complex and difficult to handle. When debugging comes in picture, sometime discussion makes debugging easy. Thinking of possible scenarios, causes and problem solving ideas varies engineers to engineers! When you stuck with debugging some issue and you don’t get any clue, don’t spend huge amount of time debugging the same issue because “debugging is not free”, instead try discussing the scenario with your team mates, you would mostly get the hint or clue to identify and fix the issues. Obviously your colleague should be supportive in natureJ. This is one of the potential places where TEAM work comes in picture!
Why the verification or design code becomes complex to handle at end of the day? What could be potential reason for this?
Customers always in hurry and wants their product ready and bug free! Critical situation comes when customer comes with their problem or with some new requirement support in design and you don’t have experienced person who have worked on this product. In this case engineers might face sleepless nights and will have to put lots and lots of efforts (because, they are not well aware of the design) to fulfill the requirement. Same requirements would have been fulfill with less amount of effort and as per expectation from client if engineers who have worked on this product are working!!
How could we avoid this type of pains?
ASIC With Ankit (Ankit Gopani)
Category: ASIC FPGA Verification