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 ASIC with Ankit

Archive for February, 2013

System Verilog: final means final !

Saturday, February 23rd, 2013

Dear Readers,

Today I would like to share some basic things on finalblock in System Verilog. This is a newly added feature in System Verilog over Verilog. Final block is good for summery information. You can have summery information printed in log file at the end of simulation.

Final block executes at the end of the simulations without delays. final block is like an initial block in SV only difference is that it occurs at the end of the simulations. Final block does not allow delays and time consuming or blocking activities and because of this reason it typically used in display statistical information on simulation result. Final block executes in zero time. Considering this nature of execution it is similar to function.Function also executes in zero time and does not allow timing related or blocking type of activities.

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The two Door Keepers: An Assertion, to make sure bad thing does not happen and coverage, to make sure Good thing happens!

Tuesday, February 19th, 2013

Dear Readers,

The two Door Keepers: An Assertion, to make sure bad thing does not happen and coverage, to make sure Good thing happens!

As we all know SVA (System Verilog Assertions) and SV Coverage are playing major role in test bench implementation which helps us achieving maximum confidence on bug free design. These components in the test environments are working as a ‘Door Keepers’! Assertions are mainly doing job to make sure bad things does not happen and Coverage is mainly doing job to make sure Good thing happens!!

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Designs or Verification Test bench becomes complex and difficult to handle at end of the day!!

Monday, February 4th, 2013

As we all know debugging is not an easy task and requires lots of attentions and effort to figure out the issues! Well, it is not at free of cost! (Debugging is not free!) This is true for both Design as well as Verification engineers.

ASIC/FPGAs are becoming more and more complex day by day and because of that RTL design and Verification environments are becoming super complex! Usually engineers start writing a code with good understanding in mind from defined specification or standards. With the complexity and sometime way of writing code makes design code / verification environment complex and difficult to handle. When debugging comes in picture, sometime discussion makes debugging easy. Thinking of possible scenarios, causes and problem solving ideas varies engineers to engineers! When you stuck with debugging some issue and you don’t get any clue, don’t spend huge amount of time debugging the same issue because “debugging is not free”, instead try discussing the scenario with your team mates, you would mostly get the hint or clue to identify and fix the issues. Obviously your colleague should be supportive in natureJ. This is one of the potential places where TEAM work comes in picture!

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NEC: CyberWorkbench
S2C: FPGA Base prototyping- Download white paper



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