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 ASIC with Ankit
Ankit Gopani
Ankit Gopani
Ankit Gopani is Lead Design Verification Engineer at SmartPlay Inc, USA. Ankit has been in the industry for more than 9 years. He pursued Diploma in E.C, B.E in Electronics and Communication and MBA in software project management.

Class – The Classic Feature – Part II

 
April 12th, 2014 by Ankit Gopani

Dear AWA Readers

Here we go with follow up post on ‘Class – The classical feature’ ! In this post I will try to cover different types of classes in brief for better understanding. There are various types of classes that we use in test bench development.  The usage of class is depends on the requirements.  Let’s understand what different types of classes that we use in system verilog.

Different types of classes:
  1. Basic Class
  2. Abstract Class
  3. Parameterised Class
  4. Nested Class
  5. Typedef Class

Basic Class:

Basic class is covered in my last post, you can refer It from here. Read the rest of Class – The Classic Feature – Part II

“Class” – The Classical feature !!

 
October 31st, 2013 by Ankit Gopani

Dear Readers,

Let’s understand the classical feature of System Verilog ‘Class‘. Here I would try to explain on class feature, object properties and methods, object instantiation, class methods polymorphism and constructor concept.

What is class and why is it classical :) Lets understand

  • Class is a generalization of the data type concept and central to the Object Oriented Programming.
  • A class is a type that includes data and subroutines like functions and tasks.
  • The class properties and methods creates a capabilities of some kind of objects.

Read the rest of “Class” – The Classical feature !!

System Verilog Queues which can shrink and grow !

 
May 18th, 2013 by Ankit Gopani

Dear Readers,

System Verilog has new data type called ‘queue’ which can grow and shrink. With SV queue, we can easily add and remove elements anywhere that is the reason we say it can shrink and grow as we need. Queues can be used as LIFO (Last In First Out) Buffer or FIFO (First In First Out) type of buffers.

Each element in the queue is identified by an ordinal number that represents its position within the queue, with 0 representing the first element and $ represents the last element.

The size of the queue is variable similar to dynamic array but queue may be empty with zero element and still its a valid data structure.

Lets take a few examples to understand queue operation with different methods we have in system verilog.

Read the rest of System Verilog Queues which can shrink and grow !

Verilog to System Verilog : A Successful journey towards SV

 
May 1st, 2013 by Ankit Gopani

Dear Readers,

We have been using standard languages and methodologies for ASIC/FPGA design and Verification activities. We as an engineer must know on history of verification activities. Today we mostly work on verification standard languages like System Verilog. The whole industry is moving to accept this language with few methodologies (RVM, VMM, AVM, OVM, UVM etc…) as their standards for new and existing product development and verification.

Now since we use the industry standard languages like VHLD, Verilog, and System Verilog, we must know and understand history and importance of Verification languages. 

Let’s understand how we reached to a System Verilog usage? What are the other different verification languages engineers were using in past few decades? How did they start their usage from Verilog to System Verilog for verification? Let’s go back to history and understand these questions.

Read the rest of Verilog to System Verilog : A Successful journey towards SV

System Verilog : Which final is Final ?

 
March 14th, 2013 by Ankit Gopani

Dear Reader,

Recently I posted one blog post “System Verilog Final Means Final !”

As we all know final means final in system Verilog, Final block will get called at the end of the simulation before $finish. Now with this understanding we can have few questions. Recently few engineers have asked me some questions and thought answering those questions. Questions asked are listed below

  1. Is multiple final block is allowed in System Verilog?
  2. If yes, what will be the execution order in simulation, which final is final?

Here are the answers to this questions :

Multiple final blocks are allowed in system Verilog, you can define multiple final block in your testbench. Some time you might require to use final blocks in different places of environment. Here we need to understand one most important thing on final block is that, final blocks are called at the end of the simulation before $finish. It is like a calling a function which executes in zero simulation time.

Read the rest of System Verilog : Which final is Final ?

System Verilog: final means final !

 
February 23rd, 2013 by Ankit Gopani

Dear Readers,

Today I would like to share some basic things on finalblock in System Verilog. This is a newly added feature in System Verilog over Verilog. Final block is good for summery information. You can have summery information printed in log file at the end of simulation.

Final block executes at the end of the simulations without delays. final block is like an initial block in SV only difference is that it occurs at the end of the simulations. Final block does not allow delays and time consuming or blocking activities and because of this reason it typically used in display statistical information on simulation result. Final block executes in zero time. Considering this nature of execution it is similar to function.Function also executes in zero time and does not allow timing related or blocking type of activities.

Read the rest of System Verilog: final means final !

The two Door Keepers: An Assertion, to make sure bad thing does not happen and coverage, to make sure Good thing happens!

 
February 19th, 2013 by Ankit Gopani

Dear Readers,

The two Door Keepers: An Assertion, to make sure bad thing does not happen and coverage, to make sure Good thing happens!

As we all know SVA (System Verilog Assertions) and SV Coverage are playing major role in test bench implementation which helps us achieving maximum confidence on bug free design. These components in the test environments are working as a ‘Door Keepers’! Assertions are mainly doing job to make sure bad things does not happen and Coverage is mainly doing job to make sure Good thing happens!!

Read the rest of The two Door Keepers: An Assertion, to make sure bad thing does not happen and coverage, to make sure Good thing happens!

Designs or Verification Test bench becomes complex and difficult to handle at end of the day!!

 
February 4th, 2013 by Ankit Gopani

As we all know debugging is not an easy task and requires lots of attentions and effort to figure out the issues! Well, it is not at free of cost! (Debugging is not free!) This is true for both Design as well as Verification engineers.

ASIC/FPGAs are becoming more and more complex day by day and because of that RTL design and Verification environments are becoming super complex! Usually engineers start writing a code with good understanding in mind from defined specification or standards. With the complexity and sometime way of writing code makes design code / verification environment complex and difficult to handle. When debugging comes in picture, sometime discussion makes debugging easy. Thinking of possible scenarios, causes and problem solving ideas varies engineers to engineers! When you stuck with debugging some issue and you don’t get any clue, don’t spend huge amount of time debugging the same issue because “debugging is not free”, instead try discussing the scenario with your team mates, you would mostly get the hint or clue to identify and fix the issues. Obviously your colleague should be supportive in natureJ. This is one of the potential places where TEAM work comes in picture!

Read the rest of Designs or Verification Test bench becomes complex and difficult to handle at end of the day!!

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