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Posts Tagged ‘verification’

Q&A with Altera: How to improve your advanced-node design productivity using Synopsys SPICE Simulation and Analysis environment

Tuesday, December 15th, 2015

Greetings,

You may have noticed from my previous post that we had a very successful event in Austin. I therefore wanted to share with you some of the technical content.  One of the aspects we cover is the increasing amount of analysis and debugging that needs to be done as design companies are moving to advanced process nodes.  While SPICE simulators keep improving performance and algorithms to allow designers to run more simulations faster, designers are left with an increasing large amount of data they need to be able to analyze and debug quickly.  Synopsys SPICE simulation environment provides a standalone solution to quickly simulate, analyze and debug advanced design nodes design to improve your productivity and reduce your design cycle.

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Optimized Synopsys-MathWorks solution for System-Level Verification

Thursday, November 14th, 2013

Verification continues to be the most challenging, expensive, and time-consuming phase in ASIC and SoC design processes today. This has been true for many years, and is expected to continue for the foreseeable future. On the business side, semiconductor design is no longer confined to “semiconductor” companies. In the past few years, many electronics, communication, and computer equipment companies have brought ASIC and SoC design activities back in-house. They now consider these designs to be competitive differentiators and crucial intellectual property rather than commodities that should be outsourced. This is – in significant part – driven by an increase in mathematical algorithmic content being engineered into signal, image and video processing, and mixed-signal designs

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Rambus drastically speed up their DFT Logic and Timing Verification in Mixed-Signal Designs using CustomSim-VCS

Thursday, August 16th, 2012

In our latest blog entries, Synopsys mixed-signal customers talked about their verification flow. Those posts described known aspects of mixed-signal environment (such as for example behavioral modeling). I wanted to highlight today a slightly different usage of Synopsys mixed signal solution among some of our customers. Using performance and ease of use of CustomSim-VCS, DFT verification engineers are able to get a considerable speedup in their simulations.

Of course, when I am referring to DFT, I am not talking about Fourier Transform, but Design For Test 🙂

Rambus is one of those customers. Working closely with Synopsys, they presented a paper on this approach. The goal was to use CustomSim-VCS to drastically improve DFT  logic and timing verification cycle-time and coverage.

In this interview, Bing Chuang from Rambus and Sumit Vishwakarma  from Synopsys share their  insights about using CustomSim –VCS  for DFT Logic and Timing Verification, the flow they architected  and the improved coverage and performance they were able to get.

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CST: Webinar series



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