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Posts Tagged ‘productivity’

Q&A with Altera: How to improve your advanced-node design productivity using Synopsys SPICE Simulation and Analysis environment

Tuesday, December 15th, 2015


You may have noticed from my previous post that we had a very successful event in Austin. I therefore wanted to share with you some of the technical content.  One of the aspects we cover is the increasing amount of analysis and debugging that needs to be done as design companies are moving to advanced process nodes.  While SPICE simulators keep improving performance and algorithms to allow designers to run more simulations faster, designers are left with an increasing large amount of data they need to be able to analyze and debug quickly.  Synopsys SPICE simulation environment provides a standalone solution to quickly simulate, analyze and debug advanced design nodes design to improve your productivity and reduce your design cycle.


S2C: FPGA Base prototyping- Download white paper

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