Open side-bar Menu
 Analog Insights

Posts Tagged ‘mixed signal; verification; DVCON 2013; systemVerilog’

Must see- User experiences tutorial on Mixed Signal Verification at DVCON 2013

Thursday, February 21st, 2013

TGIF :)

I have been asked to be co-chair at DVCON for a tutorial on Mixed Signal verification (yes, what a surprise :)) in collaboration with Martin Barnasconi, from NXP. We therefore use the best of our brain cells to put together a tutorial that highlights the latest innovation in Mixed-signal design and verification. I have listed the link below to this event:

http://dvcon.org/2013_event_details?id=144-4-T

Because DVCON is a conference focusing on functional design and verification, we recruited experts to talk about the latest advancements in mixed-signal design and verification as well as current and future challenges they foresee. Topics in this tutorial cover the application of the Universal Verification Methodology (UVM) in the mixed-signal domain, usage of VHDL-AMS or Verilog-AMS for AMS verification, and the introduction of mixed-signal features in SystemVerilog or SystemC to enable verification at the system-level. Whether you are working on extending your digital verification methodology to AMS or looking for ways to improve performance of your analog flow by leveraging digital verification techniques, this tutorial is a must see- and I am not being paid to say that :)

 

(more…)

CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy