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Rambus drastically speed up their DFT Logic and Timing Verification in Mixed-Signal Designs using CustomSim-VCS

Thursday, August 16th, 2012

In our latest blog entries, Synopsys mixed-signal customers talked about their verification flow. Those posts described known aspects of mixed-signal environment (such as for example behavioral modeling). I wanted to highlight today a slightly different usage of Synopsys mixed signal solution among some of our customers. Using performance and ease of use of CustomSim-VCS, DFT verification engineers are able to get a considerable speedup in their simulations.

Of course, when I am referring to DFT, I am not talking about Fourier Transform, but Design For Test :)

Rambus is one of those customers. Working closely with Synopsys, they presented a paper on this approach. The goal was to use CustomSim-VCS to drastically improve DFT  logic and timing verification cycle-time and coverage.

In this interview, Bing Chuang from Rambus and Sumit Vishwakarma  from Synopsys share their  insights about using CustomSim –VCS  for DFT Logic and Timing Verification, the flow they architected  and the improved coverage and performance they were able to get.


S2C: FPGA Base prototyping- Download white paper

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