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Posts Tagged ‘CustomSim ERC CCK verification reliability SOA dynamic static check’

Q&A with ST-Ericsson: Latest ERC flow innovations using CustomSim CCK for optimal verification coverage

Monday, July 2nd, 2012

Circuit design implementation has become increasingly complex in deep submicron technologies. Multiple processor cores, I/Os peripherals, complex analog circuits, and logic are now being implemented onto the same chip. Ensuring product reliability to meet design goals and to achieve good yield has become a crucial step in today design cycle. With complex IP, system integration, and multiple power domains, you need an extremely flexible and powerful EDA solution to tackle those circuit verification demands.

Synopsys CustomSim Circuit Check (CCK) provides this solution:  it helps users to avoid wasted simulation time by finding design and performance problems automatically, reporting potential problems in a circuit before running simulation. You can find more information at

http://www.synopsys.com/Tools/verification/AMSVerification/Reliability/Pages/CircuitCheck.aspx

I therefore wanted to give you more insights on Synopsys CCK and how our customers are addressing those challenges.  ST-Ericsson presented at our European SNUG event a very innovative flow they developed in tight collaboration with Synopsys using CCK Dynamic ERC (Electrical Rule Checking) for an optimal verification coverage.

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