Senior Product Marketing Manager for circuit simulation products at Synopsys.
AMD talks about advanced regression and verification for Mixed-Signal Designs using CustomExplorerUltra
August 9th, 2012 by Hélène Thibiéroz
If you read my blog or other EDA related blogs, you probably have already figured out that verification, specifically for mixed-signal designs, is getting increasingly complex. Different variables have to be taken in consideration: complexity of your design environment or topology, high-volume of regression runs, simulation speed are just a few of those . The verification methodology has also to support multiple languages, and work with different netlist formats available across the industry. As such, there is a crucial need for an integrated mixed-signal verification environment that focuses on functionality, reliability, and performance.
Well, today is your lucky day, Synopsys has such a tool :). CustomExplorer™ Ultra (CXU), is a GUI- and netlist-based verification platform that helps automate Verification regression tests without manually creating different configuration files or scripts.
STE talks about their mixed-signal verification using CustomSim-VCS and VHDL real number modeling for AMS designs
July 31st, 2012 by Hélène Thibiéroz
Verification is getting to be a more and more critical step in today IC designs. As more and more analog designs evolve into mixed-signal ones, verification methodologies and strategies need to be further refined and improved to address new challenges. While the verification of the logic part, mostly implemented in Verilog and VHDL, has gained momentum, the analog part suffers from not being supported by this language. To speed up the verification of the analog part (SPICE, Verilog-A(MS), VHDL-AMS), innovation is needed.
In our previous post, we talked about VerilogAMS, which is one approach. In this post, I wanted to talk about an other approach, Real Number Modeling, and highlight the efficient solution developed co-jointly by ST Ericsson and Synopsys, which is based on Synopsys CustomSim-VCS VHDL- Real Number flow. Using this flow, ST-E was able to boost simulation performance and increase verification coverage of their most complex AMS chips.
Both flows (VerilogAMS and Real Number Modeling) are fully supported by Synopsys.
July 10th, 2012 by Hélène Thibiéroz
As a chair(wo)man for the AMS track at DesignCon (yes I know, you heard it before ), I just want to inform you that the call for abstracts is now open for DesignCon 2013:
You have until August 17,2012 to submit your abstract. In order to get innovative content, our AMS technical committee selected a large range of topics representative of actual and upcoming challenges faced by AMS engineers (I have included this list below). You can submit your abstract using the above link.
Feel free to contact me anytime if you have any questions, we look forward to reviewing your abstracts.
You can find some related information to last year tutorial and event at:
I am also working on a tutorial and panel focusing on Mixed Signal Verification, more to come later…
Analog, RF, and Mixed-Signal Design and Verification sample topics
Design & verification methodologies
Simulation algorithms and techniques
Mixed-signal behavioral modeling approaches
Verilog-A, Verilog-AMS, VHDL-AMS, SystemVerilog, SystemC-AMS, etc.
Mixed-domain design and verification solutions
MEMS, electro-optics, mechatronics, etc.
Mixed-domain/mixed-language verification strategies
Analog and RF IP: selection, integration, and modeling
Coverage, metrics, and closure management
Power distribution & management
Yield analysis, Monte Carlo methods, and optimization approaches
On-chip inductors: design and modeling
RLCK extraction: post-layout flows and strategies
Noise analysis and prediction: substrate, spurious, random
Variability effects and statistical analyses
Q&A with ST-Ericsson: Latest ERC flow innovations using CustomSim CCK for optimal verification coverage
July 2nd, 2012 by Hélène Thibiéroz
Circuit design implementation has become increasingly complex in deep submicron technologies. Multiple processor cores, I/Os peripherals, complex analog circuits, and logic are now being implemented onto the same chip. Ensuring product reliability to meet design goals and to achieve good yield has become a crucial step in today design cycle. With complex IP, system integration, and multiple power domains, you need an extremely flexible and powerful EDA solution to tackle those circuit verification demands.
Synopsys CustomSim Circuit Check (CCK) provides this solution: it helps users to avoid wasted simulation time by finding design and performance problems automatically, reporting potential problems in a circuit before running simulation. You can find more information at
I therefore wanted to give you more insights on Synopsys CCK and how our customers are addressing those challenges. ST-Ericsson presented at our European SNUG event a very innovative flow they developed in tight collaboration with Synopsys using CCK Dynamic ERC (Electrical Rule Checking) for an optimal verification coverage.
June 26th, 2012 by Hélène Thibiéroz
A few months ago at 2012 San Jose SNUG, I attended the FinFET keynote speech by Professor Chenming Hu, the Father of FinFET. Professor Hu’s speech was exceptionally well received by the audience (more than 400 people). I had the opportunity to meet him . Because his keynote was really informative and because FinFET technology is an innovative and captivating subject, I asked Professor Hu to share more of his insights and vision on the FinFET technology with us.
Dr. Chenming Hu has been called the Father of 3D Transistors for leading FinFET development in 1999. Intel is the first company to use FinFET in 2011 production calling it the most radical shift in semiconductor technology in over 50 years. Other companies are expected to follow. IEEE called him “Microelectronics Visionary” and noted his pioneering contributions to integrated circuit reliability in presenting him the Nishizawa Medal for “achievements critical to producing smaller yet more reliable and higher-performance integrated circuits”. US Semiconductor Industry Association thanked him for research leadership for “advancement of the electronics industry and of our national economy”. IEEE EDS gave him the 2011 Education Award for “distinguished contributions to education and inspiration of students, practicing engineers and future educators”.
He has authored four books including a new textbook and 900 research papers, and has been granted over 100 US patents. He is a fellow of the IEEE and an Honorary Professor of CAS Microelectronics Institute and National Chiao Tung University. His many awards include the 2007 Andrew Grove Award for device reliability research and the 2002 Donald Pederson Award in Solid State Circuits for the BSIM standard transistor model. The 2009 SRC Aristotle Award recognized him as an influential mentor to many outstanding students. He has received UC Berkeley’s highest honor for teaching — the Berkeley Distinguished Teaching Award. He is researching green tunnel transistor for ultra-low-power electronics.
June 21st, 2012 by Hélène Thibiéroz
The day you all have been waiting for has finally arrived; our Analog Insights blog is Back! Our mission is to create an interactive place where information can be shared and discussed among our design community, from a pure Analog spice-level circuit to an advanced SOC design.
Because Synopsys Custom and AMS tools portfolio is extremely diverse and comprehensive, our range of topics will vary from analog, RF, to mixed signal from a simulation and design angle. The goal of Analog Insights is to also provide accurate information about the flows or solutions that would benefit our end-users and improve performance and productivity.
For example, you will be able to find: