Verification is getting to be a more and more critical step in today IC designs. As more and more analog designs evolve into mixed-signal ones, verification methodologies and strategies need to be further refined and improved to address new challenges. While the verification of the logic part, mostly implemented in Verilog and VHDL, has gained momentum, the analog part suffers from not being supported by this language. To speed up the verification of the analog part (SPICE, Verilog-A(MS), VHDL-AMS), innovation is needed.
In our previous post, we talked about VerilogAMS, which is one approach. In this post, I wanted to talk about an other approach, Real Number Modeling, and highlight the efficient solution developed co-jointly by ST Ericsson and Synopsys, which is based on Synopsys CustomSim-VCS VHDL- Real Number flow. Using this flow, ST-E was able to boost simulation performance and increase verification coverage of their most complex AMS chips.
Both flows (VerilogAMS and Real Number Modeling) are fully supported by Synopsys.