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Q&A with Altera: How to improve your advanced-node design productivity using Synopsys SPICE Simulation and Analysis environment

Tuesday, December 15th, 2015


You may have noticed from my previous post that we had a very successful event in Austin. I therefore wanted to share with you some of the technical content.  One of the aspects we cover is the increasing amount of analysis and debugging that needs to be done as design companies are moving to advanced process nodes.  While SPICE simulators keep improving performance and algorithms to allow designers to run more simulations faster, designers are left with an increasing large amount of data they need to be able to analyze and debug quickly.  Synopsys SPICE simulation environment provides a standalone solution to quickly simulate, analyze and debug advanced design nodes design to improve your productivity and reduce your design cycle.


Great success for Synopsys Austin AMS SIG event

Thursday, December 3rd, 2015

Happy post Turkey-day Thursday !

Because we had a very successful event during ICCAD where more than 120 persons came to learn about the latest technical features offered by Synopsys AMS tools, I wanted to give you a small technical summary for our first Synopsys Austin AMS SIG event.

We started from SoC level with mixed-signal verification to end with device modeling and more specifically FinFET modeling.


Optimized Synopsys-MathWorks solution for System-Level Verification

Thursday, November 14th, 2013

Verification continues to be the most challenging, expensive, and time-consuming phase in ASIC and SoC design processes today. This has been true for many years, and is expected to continue for the foreseeable future. On the business side, semiconductor design is no longer confined to “semiconductor” companies. In the past few years, many electronics, communication, and computer equipment companies have brought ASIC and SoC design activities back in-house. They now consider these designs to be competitive differentiators and crucial intellectual property rather than commodities that should be outsourced. This is – in significant part – driven by an increase in mathematical algorithmic content being engineered into signal, image and video processing, and mixed-signal designs


Must see- User experiences tutorial on Mixed Signal Verification at DVCON 2013

Thursday, February 21st, 2013


I have been asked to be co-chair at DVCON for a tutorial on Mixed Signal verification (yes, what a surprise :)) in collaboration with Martin Barnasconi, from NXP. We therefore use the best of our brain cells to put together a tutorial that highlights the latest innovation in Mixed-signal design and verification. I have listed the link below to this event:

Because DVCON is a conference focusing on functional design and verification, we recruited experts to talk about the latest advancements in mixed-signal design and verification as well as current and future challenges they foresee. Topics in this tutorial cover the application of the Universal Verification Methodology (UVM) in the mixed-signal domain, usage of VHDL-AMS or Verilog-AMS for AMS verification, and the introduction of mixed-signal features in SystemVerilog or SystemC to enable verification at the system-level. Whether you are working on extending your digital verification methodology to AMS or looking for ways to improve performance of your analog flow by leveraging digital verification techniques, this tutorial is a must see- and I am not being paid to say that 🙂



MTV 2012 Mixed Signal Verification Panel – Can Mixed Signal Verification be done with no analog solver ?

Monday, December 31st, 2012

Well, it has been a while, hasn’t it? No, I have not been lazy, I have just been busy working on Synopsys amazing portfolio of simulators.

I attended last week MTV (Microprocessor Test and Verification) conference in Austin (and no, that was not a music festival, sorry..), and participated in a panel on Mixed Signal Verification:

The panel included professionals from Design Houses, EDA vendors as well as Universities. Our goal was really to discuss about Digital verification extended to Mixed signal domain and current advantages and pitfalls in both simulation and environment through two main questions (I have listed those below).


Q&A : How ST optimized their validation flow and decreased turn-around time by 8X using Synopsys Custom Explorer

Thursday, November 1st, 2012

You may have watched the previous video I posted on CustomExplorer Ultra (if not, it is not too late :)). A very interesting feature of this tool is its Waveform comparison capability.

This utility allows you to compare two sets of simulation runs in batch and produce a text report of the differences. In just a few words, you define a simple rules file that controls the comparisons, what signals are to be compared and the tolerances of the comparisons. Using sample-based comparison techniques, CXU compares golden-to-target simulation results and provides validation results.  You are going to tell me, nothing really revolutionary here.. So let me just give you finer details 🙂


Optimize your Mixed Signal Verification Environment – Part 1

Friday, October 5th, 2012

With increasing complexity of mixed-signal designs comes a more and more expensive coverage scheme for verification, from the analog as well as the digital side. Finding a verification cockpit combining ease-of-use, performance and required features for both Analog and Digital is therefore not a trivial task.

If you think about it, you need an environment able to support both Analog and Digital domains, all potential configurations as well as various language extensions (SPICE, Verilog, VHDL, VerilogA, VerilogAMS,….). You also need to cover a large design space, requiring an efficient way to run multi tests in parallel, to display both analog and digital results simultaneously and troubleshoot any accuracy/convergence issues.

With that in mind, I wanted to further develop on Synopsys CustomerExplorer Ultra and how this platform fits today verification needs. But rather than just giving you a list of features or a datasheet, I wanted to focus on key points of CXU using small videos. I know, I am a nice person 🙂

I have therefore asked several CXU experts to demo some of those features. In this 4 minute video, Manu Pillai is showing us the spice debugging features of CustomExplorer Ultra’ s Connection View:

Multi-net connectivity/Full schematic display: CXU’s Connection View is highly interactive. It accepts the designs in the netlist format and allows the user to display the signal path relevant for the debugging. It is capable of showing the connectivity of multiple nets and complete schematic, so that user can visualize their netlist .

Waveform Cross Probing: User can link the existing or newly created waveform file with the Connection View and cross probe the signals. This is very useful for the debugging purpose.

Parameter report and W/L report: Netlists may have lot of parameters with expressions and CXU will evaluate these expressions and gives the parameter report. The W/L report gives the width & length information of all the MOS devices in the design. These reports will be useful to identify unreasonable parameter definitions or width and length values.

Enjoy the movie 🙂




Call for papers for IEEE 2013 WMED conference

Wednesday, September 26th, 2012

Just a quick call for papers for 2013 WMED, which is scheduled to take place on Friday, April 12, 2013 in the Student Union Building of Boise State University.

Synopsys is currently a platinum sponsor for 2013 IEEE Workshop on Microelectronics and Electron Devices (WMED). This conference provides a forum for reviewing and discussing all aspects of microelectronics including processing, electrical characterization, design, and new device technologies. This workshop will consist of invited talks, contributed papers, tutorials, as well as a poster session throughout the afternoon.

I therefore asked Tim Hollis, general chair of WMED to provide us with more insights on this conference.


Rambus drastically speed up their DFT Logic and Timing Verification in Mixed-Signal Designs using CustomSim-VCS

Thursday, August 16th, 2012

In our latest blog entries, Synopsys mixed-signal customers talked about their verification flow. Those posts described known aspects of mixed-signal environment (such as for example behavioral modeling). I wanted to highlight today a slightly different usage of Synopsys mixed signal solution among some of our customers. Using performance and ease of use of CustomSim-VCS, DFT verification engineers are able to get a considerable speedup in their simulations.

Of course, when I am referring to DFT, I am not talking about Fourier Transform, but Design For Test 🙂

Rambus is one of those customers. Working closely with Synopsys, they presented a paper on this approach. The goal was to use CustomSim-VCS to drastically improve DFT  logic and timing verification cycle-time and coverage.

In this interview, Bing Chuang from Rambus and Sumit Vishwakarma  from Synopsys share their  insights about using CustomSim –VCS  for DFT Logic and Timing Verification, the flow they architected  and the improved coverage and performance they were able to get.


AMD talks about advanced regression and verification for Mixed-Signal Designs using CustomExplorerUltra

Thursday, August 9th, 2012

If you read my blog or other EDA related blogs, you probably have already figured out that verification, specifically for mixed-signal designs, is getting increasingly complex. Different variables have to be taken in consideration: complexity of your design environment or topology, high-volume of regression runs, simulation speed are just a few of those . The verification methodology has also to support multiple languages, and work with different netlist formats available across the industry. As such, there is a crucial need for an integrated mixed-signal verification environment that focuses on functionality, reliability, and performance.

Well, today is your lucky day, Synopsys has such a tool :). CustomExplorer™ Ultra (CXU), is a GUI- and netlist-based verification platform that helps automate Verification regression tests without manually creating different configuration files or scripts.


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