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Archive for the ‘Mixed Signal’ Category

Optimized Synopsys-MathWorks solution for System-Level Verification

Thursday, November 14th, 2013

Verification continues to be the most challenging, expensive, and time-consuming phase in ASIC and SoC design processes today. This has been true for many years, and is expected to continue for the foreseeable future. On the business side, semiconductor design is no longer confined to “semiconductor” companies. In the past few years, many electronics, communication, and computer equipment companies have brought ASIC and SoC design activities back in-house. They now consider these designs to be competitive differentiators and crucial intellectual property rather than commodities that should be outsourced. This is – in significant part – driven by an increase in mathematical algorithmic content being engineered into signal, image and video processing, and mixed-signal designs


Must see- User experiences tutorial on Mixed Signal Verification at DVCON 2013

Thursday, February 21st, 2013


I have been asked to be co-chair at DVCON for a tutorial on Mixed Signal verification (yes, what a surprise :)) in collaboration with Martin Barnasconi, from NXP. We therefore use the best of our brain cells to put together a tutorial that highlights the latest innovation in Mixed-signal design and verification. I have listed the link below to this event:

Because DVCON is a conference focusing on functional design and verification, we recruited experts to talk about the latest advancements in mixed-signal design and verification as well as current and future challenges they foresee. Topics in this tutorial cover the application of the Universal Verification Methodology (UVM) in the mixed-signal domain, usage of VHDL-AMS or Verilog-AMS for AMS verification, and the introduction of mixed-signal features in SystemVerilog or SystemC to enable verification at the system-level. Whether you are working on extending your digital verification methodology to AMS or looking for ways to improve performance of your analog flow by leveraging digital verification techniques, this tutorial is a must see- and I am not being paid to say that 🙂



Behavioral Modeling Approaches for Analog, Mixed-Signal, and RF- Latest trends from experts at our DesignCon AMS tutorial

Tuesday, January 22nd, 2013

As a chair(wo)man for the AMS track at DesignCon, I wanted to talk about a special event I put together for DesignCon AMS track. I specifically created this year a tutorial to emphasize on behavioral modeling. Because DesignCon is a broad conference, going from chip design to signal integrity and board level design, I wanted to cover different modeling techniques available for Analog, Mixed Signal and/or RF. My end goal was not only to give some general insights to someone new to behavioral modeling  or someone expert for one type(for example VerilogAMS) that would like to get exposed to other techniques (such as Matlab/Simulink or real number modeling) but also to correlate/compare those modeling techniques by presenting pros and cons of each approach.



The tutorial can be accessed at:


TrueCircuits: IoTPLL

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