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Hélène Thibiéroz
Hélène Thibiéroz
Senior Product Marketing Manager for circuit simulation products at Synopsys.

Q&A with Altera: How to improve your advanced-node design productivity using Synopsys SPICE Simulation and Analysis environment

 
December 15th, 2015 by Hélène Thibiéroz

Greetings,

You may have noticed from my previous post that we had a very successful event in Austin. I therefore wanted to share with you some of the technical content.  One of the aspects we cover is the increasing amount of analysis and debugging that needs to be done as design companies are moving to advanced process nodes.  While SPICE simulators keep improving performance and algorithms to allow designers to run more simulations faster, designers are left with an increasing large amount of data they need to be able to analyze and debug quickly.  Synopsys SPICE simulation environment provides a standalone solution to quickly simulate, analyze and debug advanced design nodes design to improve your productivity and reduce your design cycle.

Sireesha Dhulipati

Sireesha Dhulipati

Sireesha Dhulipati presented their usage for advanced node designs and how they are currently leveraging SAE to automate the analysis process and significantly increase their design productivity.

  1. What are Altera needs in term of analog mixed-signal verification? Which specific challenges are you faced with in term of analyzing and debugging more and more complex designs?

High-speed memory makes design very challenging due to signal integrity, skew, and noise management issues. These high speed memory devices require very tight timing margin requirements between the data and clock. These tight timing requirements and very stringent board requirements introduce several design challenges. With the increase in the edge rates of I/Os associated with a memory interface, the design of the link between the input buffer and the output buffer is becoming very challenging.  Faster edges of the signals are very sensitive to any discontinuities on the transmission path.  Signal integrity issues such as reflections/ringing due to high input capacitance and noise due to power/ground oscillations are becoming more pronounced, requiring a thorough evaluation.

In addition, when moving to advanced node technologies, we are facing with more and  more challenges in running and analyzing transistor-level designs  as we have multiple test benches with multiple formats with different simulation setups and tightening constraints to meet our yield requirements which requires more MC simulations to be run and analyzed.

Data post processing is also a challenge as we analyze tons of data. We also do a lot of mixed signal verification and we need an environment for easier processing, viewing and probing of both analog and digital results

For these reasons, using the advanced GUI SAE becomes a crucial need for delivering high quality designs in time with a low TTM.

  1. What motivated Altera to start using SAE? Which specific technical features and flows were especially useful in reducing analysis time?

SAE is an advanced user interface which supports versatile simulation setup, custom scripting capabilities and also post processing features for complex debugging which increases productivity.

Some of the specific technical features would include

  • MC simulations with multiple PVT corners and sweeping across some of the design variables.
  • Multiple test bench support and parasitic simulations
  • Mixed signal simulations
  • Post processing capabilities – data mining, charts cross probing, report generation

Synopsys SPICE simulation Analysis Environment

     3, Can you talk more about the type of verification you did?

At Altera we do multi-dimensional verification – our designs are so complex that we can’t anymore use simple corners. We have to use complex corners configurations with multiple global corners, corner groups and sweeping across multiple test-benches that require a more advanced GUI to also enable all the post processing features. SAE enables these features to do our multi-dimensional verification.

Some of the types of designs we used are various blocks in PLL, CDR in the transmitter and receiver sections. Since these are highly sensitive analog blocks, we do run a lot of Monte Carlo simulations with local and global variations we also need to run advanced noise analysis for Jitter and eye diagram plotting.  Some of the post layout designs would have a size of around 500k MOSFET’s in them to evaluate which needs a good GUI to probe different parts of the design after simulations and analysis on them.

        4. What was your overall assessment of SAE and the main differentiating points versus other tools?

While evaluating SAE, we used 20 test benches on 13 circuits selected with the following characteristics

  • Circuits: PLLs, bandgaps, clock networks, loop filters, M20K, charge pump, serializer, etc.
  • Processes: 20nm and 14nm
  • Analysis: DC, AC, transient, and Monte Carlo
  • Measurements: Delay, voltage, current, gain, bandwidth, mean, and standard deviation
  • Pre and post-layout designs

Features that were compared with the other GUI’s– post processing capabilities, mixed signal verification, advanced noise analysis and post layout simulations setup, huge Monte Carlo data handling and graphic way of displaying with Worst-case corner analysis, possible ways of improving the yield of the circuit.

After testing those circuits with complex corner definitions and tons of Monte Carlo analysis with multiple sweeps that generate a lot of data to post process, we found that SAE stand out as a leader versus other commercial GUI’s by providing advanced capabilities (such as data mining, scatterplot capabilities,…) to quickly and efficiently simulate and analyze very large amount of data.

Thank you Sireesha, it was a pleasure to have you as a speaker at our Austin AMS SIG event.

If you are interested in hearing more about Synopsys SAE capabilities, please contact me or your Synopsys account person anytime.

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