Senior Product Marketing Manager for circuit simulation products at Synopsys.
Great success for Synopsys Austin AMS SIG event
December 3rd, 2015 by Hélène Thibiéroz
Happy post Turkey-day Thursday !
Because we had a very successful event during ICCAD where more than 120 persons came to learn about the latest technical features offered by Synopsys AMS tools, I wanted to give you a small technical summary for our first Synopsys Austin AMS SIG event.
We started from SoC level with mixed-signal verification to end with device modeling and more specifically FinFET modeling.
Our first speaker was Bramha Marathe, from Qualcomm. Technologies Inc. He is currently director of engineering, Central Verification & Validation Team at Qualcomm Technologies Inc . He gave to the audience a great presentation on how his design teams extended digital verification to analog using VCS AMS. His first key point was a seamless migration to AMS verification by being able to minimally change testbench and by taking advantage of VCS AMS superior performance features (save and restore for example) for regression. His second topic was the capability to adopt the best of digital verification methodology for mixed-signal (assertions, functioaln coverage) that are being offered by AMS testbench technology. His last key point was the capability to extend low power verification to AMS (by using VCS AMS UPF extension and power calculation checks ).
Our second speaker was Mandeep Singh, custom circuit CAD manager at Samsung Austin R&D center. He demonstrated how memory simulation challenges increase when moving to advanced technology nodes and more specifically FinFET designs. Factors such as increasing extracted netlist complexity, larger number of signoff corners going from 32nm to 10nm drastically impact fast turn-around time at low accuracy cost to ensure time to market. Mandeep demonstrated how his team was able to leverage FineSim SPICE continuous performance improvements from 32nm to 14nm to keep this TTM constant while moving to advanced process nodes.
Our third speaker was Sireesha Dhulipati from Altera Corporation. While the two first speakers highlighted Synopsys simulators technical features and performance improvments, Sireesha demonstrated how Altera successfully used Synopsys SPICE simulation environment (SAE) to drastically improve advanced-node design productivity. They tested several features (advanced test-bench support, large scale multi-dimensions verification, statistical analysis and data mining, WaveView capability for more advanced measurement definition) on various circuits (SerDes, PLL’s, clock networks, filters with pre and post layout simulations for large scale verification and memory designs for efficient visualization of yield and data correlation) and presented the successful results of their evaluations.
Our last speaker closed our event with the foundation of AMS simulation, device modeling, and more specifically FinFET modeling. Joddy Wang, senior R&D manager at Synopsys responsible for the device modeling team, covered in detailes FinFET device modeling challenges and Synopsys solution, optimized for both performance and accuracy.
So overall great success and great technical presentations, feel free to contact me anytime if you have any questions.
With that, I wish to all you a very Happy Thanksgiving.
Speaker LinkedIn profiles:
Tags: advanced nodes, AMS, digital verification, FinFET, mixed-signal verification