Analog Insights

Hélène Thibiéroz
Hélène Thibiéroz
Senior Product Marketing Manager for circuit simulation products at Synopsys.

Optimized Synopsys-MathWorks solution for System-Level Verification

 
November 14th, 2013 by Hélène Thibiéroz

Verification continues to be the most challenging, expensive, and time-consuming phase in ASIC and SoC design processes today. This has been true for many years, and is expected to continue for the foreseeable future. On the business side, semiconductor design is no longer confined to “semiconductor” companies. In the past few years, many electronics, communication, and computer equipment companies have brought ASIC and SoC design activities back in-house. They now consider these designs to be competitive differentiators and crucial intellectual property rather than commodities that should be outsourced. This is – in significant part – driven by an increase in mathematical algorithmic content being engineered into signal, image and video processing, and mixed-signal designs

With the increasing complexity of those designs, there is a crucial need today for a system-level verification methodology:   verification engineers need to be able to take a system they designed at a higher level of abstraction and verify it against their RTL and mixed-signal flows, allows them to have increased confidence in their design, and identify and fix defects or bugs.

MathWorks and Synopsys have been developing new capabilities to significantly improve productivity in these verification activities, including deployment of models to SystemVerilog to provide a more integrated verification workflow.

As such, I wanted to talk today about this co-joint effort led by Mathworks and Synopsys to provide a unique solution to deliver such methodology. I have asked Arun Mulpur from MathWorks and Rebecca Lipon from Synopsys VG to give us more insights about this solution and its benefits.

Arun Mulpur has been with MathWorks since 2002 and currently manages a team of industry marketing managers that focus on communications, electronics, semiconductors, medical devices and robotics industries. He works with key customers worldwide to discuss their application requirements and workflow gaps, and addressing them in collaboration with key EDA partners.

 

 

Rebecca Lipon is currently the Senior Product Marketing Manager for Synopsys Verification products. Rebecca has over a decade of experience in the semiconductor industry with engineering roles at Synopsys, SGI, and ATI. She holds a BS in Electrical Engineering & Computer Science from MIT.

 

 

 

 Helene> Arun, Rebecca: Can you give us some background on this methodology? What were the driving factors of this successful collaboration between Mathworks and Synopsys?

Arun: Engineering teams predominantly use MATLAB, Simulink, and Model-Based Design for their algorithm and behavioral designs. They create executable specifications, golden reference models, and high level algorithmic implementations in MATLAB and Simulink and use them throughout the system design, prototyping, implementation, and verification stages. As a consequence of the above trends, these engineering teams are looking for ways to integrate their MATLAB and Simulink models in with their core digital, analog, and mixed-signal IC design and verification flows which are predominantly based on Synopsys tools and methodologies.

Both Synopsys and MathWorks are hearing from mutual customers about the need to bridge these two worlds and enable more streamlined verification of complex ASIC and SoC designs. We have started working together to develop and provide such capabilities and are happy to announce that initial solutions are available now.

Rebecca:  Simulation remains the mode by which 60% or more of design bugs are found. By providing a tighter integration with high-level algorithmic solutions like MATLAB and Simulink with the VCS verification sign-off flow, customers have increased confidence in the logic they have designed. Model-based design solutions allow architects to fully explore their best design implementation, but without integrating it into the same verification flow used to validate the RTL implementation of the design, significant risk may exist. We are excited to provide a more usable and robust solution for our joint customers to reduce their risk and increase their confidence in their final design implementation.

Helene> Arun, you have been deeply involved with the development of Synopsys/Mathworks flow, can you give us more technical insights on the two flows we currently support?

Arun:

For Interactive debugging and unit-level testing: if the primary need is for verification of digital algorithms or system components, and a part of the Device Under Test (DUT) or test bench is expressed in VHDL or Verilog, we recommend cosimulation as the first step during initial interactive design and unit testing stages. In this scenario, both MATLAB & Simulink and VCS simulation engines are running simultaneously – either on the same machine or on different servers in a network – and executing different parts of the test bench and the DUT run in their own environment. C/C++ portions can run in either environment depending on how the simulation is configured. This workflow ensures that IP components have been verified according to the golden reference or executable specification.

For production verification and validation: In this scenario, engineers model, simulate, and verify digital or mixed-signal algorithms or system components in Simulink and MATLAB. To integrate these IP components and test benches with other components in VCS, Simulink can export these models as C code with SystemVerilog wrappers. These components can be used in VCS along with other SystemVerilog components or test benches for verification of the complete system design. In this case, when the simulation executes in VCS, Simulink and MATLAB simulation engines are not involved, and all the components run natively and exclusively in VCS.

 

Helene> How do you see this flow evolve moving forward based on how digital and mixed signal verification are evolving? What would be next?

Arun:

To learn more: The cosimulation and System Verilog export capabilities are both available now. Please contact MathWorks if you want to evaluate them or need more information. Additionally, one of the use cases that we are hearing from our mutual customers is the need for analog cosimulation interface between Simulink and Synopsys environments such as HSIM. If this use case is of interest, and you are interested in working together with Synopsys and MathWorks to explore possible solutions within the framework of a pilot project, please contact MathWorks.

Rebecca: We have invested significantly in fast analog-mixed signal cosimulation, native low power simulation, and many other advanced flows including this new cosimulation mode with MATLAB/Simulink in order to address the increasing complexity of our customers’ designs. Enhancements in AMS methodology and language support, as well as increased automation to allow users to cover more complex scenarios as efficiently as possible, get better coverage across mixed-simulation modes, and leverage closer integration with key partners are all areas of focus for us moving forward. We want to minimize customer’s risk, and increase the capacity to verify their complex designs within their time-to-market windows, so we are improving performance, capacity, coverage, automation, debug, and integration.

Thanks Arun and Rebecca for this very interesting discussion. If you want to hear more about this co-joint solution, you can find some details at:

http://www.mathworks.com/products/hdl-verifier/description5.html

Feel free as well to contact me anytime. And as usual, feedback is more than welcome :)

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Categories: Analog, Behavioral modeling, Mixed Signal

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