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Archive for February, 2013

Must see- User experiences tutorial on Mixed Signal Verification at DVCON 2013

Thursday, February 21st, 2013


I have been asked to be co-chair at DVCON for a tutorial on Mixed Signal verification (yes, what a surprise :)) in collaboration with Martin Barnasconi, from NXP. We therefore use the best of our brain cells to put together a tutorial that highlights the latest innovation in Mixed-signal design and verification. I have listed the link below to this event:

Because DVCON is a conference focusing on functional design and verification, we recruited experts to talk about the latest advancements in mixed-signal design and verification as well as current and future challenges they foresee. Topics in this tutorial cover the application of the Universal Verification Methodology (UVM) in the mixed-signal domain, usage of VHDL-AMS or Verilog-AMS for AMS verification, and the introduction of mixed-signal features in SystemVerilog or SystemC to enable verification at the system-level. Whether you are working on extending your digital verification methodology to AMS or looking for ways to improve performance of your analog flow by leveraging digital verification techniques, this tutorial is a must see- and I am not being paid to say that 🙂



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