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Hélène Thibiéroz
Hélène Thibiéroz
Senior Product Marketing Manager for circuit simulation products at Synopsys.

MTV 2012 Mixed Signal Verification Panel – Can Mixed Signal Verification be done with no analog solver ?

December 31st, 2012 by Hélène Thibiéroz

Well, it has been a while, hasn’t it? No, I have not been lazy, I have just been busy working on Synopsys amazing portfolio of simulators.

I attended last week MTV (Microprocessor Test and Verification) conference in Austin (and no, that was not a music festival, sorry..), and participated in a panel on Mixed Signal Verification:

The panel included professionals from Design Houses, EDA vendors as well as Universities. Our goal was really to discuss about Digital verification extended to Mixed signal domain and current advantages and pitfalls in both simulation and environment through two main questions (I have listed those below).

This was a really good discussion as panel attendees were coming from different backgrounds and have various views and insights.  I am sharing with you some of the answers I gave earlier as well as some comments from other attendees.

Question 1:  Can mixed-signal functional verification be done effectively today without an analog simulator?  Is it possible in the future?  What pieces are missing?

Can be done – Yes; Effectively- No

Verification of mixed-signal IPs can be done using a digital simulator only. It is possible today by using technologies based on real-number modeling. Real number modeling is offered today by VerilogAMS (wreal), SystemVerilog (real) as well as VHDL (real).

In Real number modeling, analog voltages are represented as a time varying sequence of real values. So there is no voltage vs current equations or no Kirchoff’s laws being checked – the output is directly computed from the input, without taking in account currents or drive/loads conditions .

This provides satisfactory results for metrics that are digital centric, i.e. when you want to ensure the IP behaves properly, that it is functionally correct and that its features are fully exercised.  In this case,the concept of RNM provides system verification with a fraction of the time, compared to a spice/fast spice approach.

Now if you are interested in current and power consumptions, voltage and current spikes, noise, IR drops and other types of analog measures, you can’t use this approach. You will have in this case to switch to a spice or behavioral modeling approach.

As such, it is fairly common today to see a mixed flow of RNM, behavioral modeling , and transistor-levels. Designers will use RNM as much as possible to take advantage of the speed up of digital simulation and model a few blocks using behavioral modeling when accuracy is required.

While one attendee did describe a mixed signal flow based on RNM only, most attendees seem to agree on the existing limitations of a Real Number Modeling only flow for a top level Mixed Signal verification.

Now, to answer those limitations, there is more and more work in this area to extend digital model languages such as System Verilog or System C with ams constructs that would provide more and more analog capabilities.

For some of you interested in this topic, I am co-chairing a tutorial with Martin Barnasconi  (NXP Semiconductors) at DVCON on this topic (finalizing speakers as writing J)

2- Digital debug tools often ignore the mixed-signal case.  Are the current tools adequate if there is no analog simulator in the mix? Are the increasingly complicated system/board level constraints changing the answer to this question?

For an entirely digital simulation, including RNM,  digital debugging tools which allow graphing, single stepping through the code, stop-points in the code,… seem to be adequate. Kai Yang from SpringSoft (now Synopsys J) did provide a good description of their digital debug tool capabilities.

If today, the digital debug tools are getting enhanced for mixed signal, (at least for common waveform dumping or for post-processing ) , there are still many short comings.

The main reason is that analog and digital designers come from two different environments. From a  high level standpoint, you can refer to a digital flow as being tcl/script based and an analog flow as schematic driven. A digital designer will talk about coverage and regression tests while an analog designer will refer to  assertions, PVT and montecarlo. So there are clearly two different methodologies that need to be consolidated.

One example, mixed signal verification is done using either Spice testbench or Verilog/AMS testbench and correctness is assessed using waveform comparison or measurements. To answer capacity and performance needs of today mixed-signal verification, you need to do more automated self-checking test for mixed signal design: for a better productivity, digital test bench (constraint random test generation) and self-checking assertion methodology needs to be applied on mixed signal design. Synopsys fast spice simulators provide a portfolio of circuit check commands which can be used for verification ( the earlier STE blog post on CustomSim CCK is a good technical example). However, generally speaking, Spice, as a language, does not provide behavioral constructs, which are needed to write proper checker in a concise way.  Another approach is therefore to get analog voltages as real numbers from spice into digital domain and then use all digital behavioral constructs to write a proper checker. With SystemVerilog assertion language, it is then possible to write advanced checker very concisely. Synopsys has developed an AMS testbench flow based on this principle, where you apply digital techniques to optimize mixed signal verification.

So in order to answer performance and capacity needed by today mixed signal verification, EDA companies clearly to consolidate methodologies.

That’s it for now. As always, your comments/constructive criticisms are more than welcome.

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