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Posts Tagged ‘Xilinx’

It’s Time to Get Your University in Sync with Zynq: Insight From a College Student

Wednesday, August 17th, 2016

Today’s article is authored by Zach Nelson, Aldec FAE Intern. Zach is a Field Application Engineer Intern with Aldec, working in tandem with his fellow interns to develop hardware specific applications. He is set to graduate with a B.S. in Electrical Engineering from University of Nevada, Las Vegas in 2017. His field interests include ASIC Design & Solid State Electronics.

It’s time for Universities to say goodbye to their outdated FPGA boards and introduce the Xilinx® Zynq™ chip. The Zynq chip is a device which combines an FPGA fabric with a processing unit. The Zynq chip is very similar to other FPGA devices, but it does have a few key advantages and features that can enhance your designs and increase its capabilities.

What can Zynq do?

The Zynq chip has applications in the design fields related to:

  • FPGA
    • Digital Design
    • VHDL/Verilog
  • Embedded Systems
    • Robotics
    • IoT
    • Factory Automation
  • Algorithm Implementations
    • Signal Processing
    • Video/Image Processing

FPGA

The Programmable-Logic can be used in isolation of the processor which allows it to be used like a general FPGA device which can help support the topics covered in any VHDL/Verilog class as well as Digital Design. It is much easier to facilitate growth and learning in a project-based curiculum when you have a device such as the Zynq to interface with.

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To Emulate or Prototype?

Monday, May 23rd, 2016

Emulation-or-PrototypingRecently I read a Semiwiki article, Army of Engineers on Site Only Masks Weakness, in which author Jean-Marie Brunet of Mentor Graphics wrote that FPGA Prototyping requires an army of tech support engineers on-site to mask the weaknesses of FPGA prototyping flows. As the Tech Support Manager for Aldec Hardware Emulation Solutions, I have to admit I’ve never had to deploy an army onsite.

It is true that FPGA Prototyping is more challenging than emulation. Yet, for the time invested in prototype setup, developers are rewarded with a validation platform that is capable of running orders of magnitude faster than emulation.
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Reprogrammable, reprogrammable, reprogrammable: What’s great about FPGAs!

Friday, January 22nd, 2016

I-loveFPGAsI like FPGAs. My first experience with an FPGA was my university final year project where I demonstrated BIST with four Xilinx© 3000 devices; this was before FPGAs had JTAG built in. Filling up these devices with ViewDraw schematics required many hours in front of a terminal.   Fast track to today’s advances such as Xilinx UltraScale and Vivado HLx, and I hope you would agree things have moved on quite a bit.

 

Amid all this changes, however, there are some things that have remained constant. Those are the three things that are great about FPGAs: they are reprogrammable, reprogrammable, and, they are reprogrammable!

So how is this capability utilized? Here are three examples:

 

Electronic products using FPGAs:

I think it is important not look at FPGAs as some poor cousin of an ASIC. This view is from the days of LSI Logic and Xilinx marketing battles, when FPGAs were used for mopping up “glue logic”. Today an FPGA provides a massively parallel programmable digital platform with a lot of silicon IP, such as high-performance interfaces. This capability is widely used by many industries now; it is not solely driven by the volume of parts. Today, you even find FPGAs in consumer products.

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Emulation: Thinking outside of the Big Box

Tuesday, September 22nd, 2015
 
fpga_base_emulation_bIndependent FPGA Consultant, Doug Amos, has been working in programmable logic and FPGA for over 30 years. He did his first programmable logic design in the mid-80’s (around the time Aldec was born), and since then has designed or supported countless FPGA and ASIC designs.
We’ve been pleased to work with Doug over the past several months, to help tell the story of Aldec’s advanced hardware emulation and SoC and ASIC prototyping solutions. Here is a excerpt from Doug’s recent guest blog:

There’s no question; verification is a massive time drain in SoC and other chip design projects. For many years, those with deep enough pockets have turned to so-called “Big Box” emulators in order to recover some of the time lost on RTL simulation, but what about the rest of us? Is there another way to accelerate verification and reduce our overall project schedule? Yes there is; and at Aldec they call it FPGA-based Emulation.

“FPGAs; aren’t they just for prototyping?”

Sure, FPGAs are the fastest platform for prototyping, but we can also harness that speed into our verification environment, then we can achieve runtime performance 2x to 5x faster than traditional “big box” emulation systems, and all at a fraction of the cost per gate per MHz. The most significant differences between FPGA usage in prototypes and in emulation is shown in table 1.

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So, what does a vendor-independent simulator look like?

Friday, May 15th, 2015

blog_independent_simulator_051515Well, the short answer to that is, “Awesome”. Perhaps, as the product manager of a simulation tool, I’m a little biased. Not to discount the challenges that FPGA design teams face on daily basis, particularly with device complexities now going through the roof.

There was a time, not so long ago, when using a single FPGA device from one vendor was not so uncommon and simulation and verification were quite interchangeable terms. However in recent years, with the development of more complex FPGAs and an even more complex design process involving the use of IPs, VIPs and third party models , the need for vendor agnostic tools for simulation and verification has become more evident.

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Xilinx Tcl Store Integrates Aldec Simulators with Vivado IDE

Tuesday, February 24th, 2015

Xilinx-Tcl-StoreTaking a cue from the open-source community, Xilinx has launched a Tcl Store that aggregates Tcl scripts contributed by the greater development community to expand the capabilities of the Vivado® Integrated Design Environment.

All Tcl scripts contributed to the Xilinx repository are free and re-distributable under an open-source license that is based on the Berkeley Source Distribution (BSD) model. Vivado users can now download apps from the Tcl Store that include practical bundles of Tcl scripts that act just like Vivado commands, including an app that can integrate Aldec Active-HDL and Riviera-PRO tools within the Vivado design flow.

To take advantage of these pre-packaged Tcl Script apps within Vivado, users can access the Tcl Store via the Vivado IDE “Tools” menu. For the rest of this article, visit the Aldec Design and Verification Blog.

Biggest Hits and Trends from ARM TechCon

Wednesday, November 6th, 2013

The recent ARM® TechCon Conference in Santa Clara was definitely the front-runner of my favorite conferences that I attended this year. Fun, informative and filled with software engineers, physical designers, design verification teams, and hardware engineers – ARM TechCon was the place to be to learn about the latest innovations from the embedded industry. Aldec was there showcasing our HES-DVM™ and HES-7™ platforms, which enable engineers to utilize emulation and FPGA-based prototyping to verify the latest ARM designs.

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90’s Kid Active-HDL Celebrates Sweet 16

Wednesday, August 28th, 2013

As the proud Product Manager of Aldec’s  FPGA Design Simulation solution,  I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997. Active-HDL has not merely stood the test of time, it has dominated the FPGA market like a Hulk Hogan smackdown with powerful simulation performance and debugging tools.

The key to Active-HDL’s long-term success lies in Aldec’s customer-centric philosophy. Simply put, we really do listen closely to our users and invest heavily in our tools. For this reason, continued simulation performance optimizations from release to release enable users to benefit from Active-HDL’s faster simulation even as the size of FPGA designs continues to grow.

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Legacy Schematic Designs Giving you a Headache?

Tuesday, July 30th, 2013

Retargeting Legacy Designs for New Technology

Digital design has come a long way since its inception from drawing schematic on paper, to CAD tools which can be used to draw schematics, and to today’s most popular (and efficient) process of describing designs through HDLs.

I recently encountered a customer with a legacy design developed in block diagram format. If he hadn’t been an Aldec customer, he might have been stuck. Fortunately,  Aldec Active-HDL™ provides utilities for importing legacy schematic based designs from Xilinx® Foundation Series, ViewLogic™, ViewDraw™, Active-CAD™ or any schematic tools that can output an EDIF netlist.

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Aldec and Xilinx, Partnered for Success

Monday, July 8th, 2013

HW/SW Emulation and Functional Verification of Xilinx FPGAs

As an Aldec Hardware Product Manager, I make the quick flight from our home base in Las Vegas to San Jose pretty regularly. This week, I’ll be joining Aldec Software Product Manager, Dmitry Melnik, as we head out to attend “Smarter 2013”, Xilinx’ annual Technical Sales Conference.

Since Aldec is a Xilinx Alliance Member, we have been invited to showcase our solutions at their conference’s Partner Night. Working closely with key technology partnerships like Xilinx has long been the cornerstone to Aldec’s success. Our mutual customers have benefited from these alliances, the result of hard work, open communication and close interaction between our teams.

Most recently, we’ve been syncing with our counterparts at Xilinx to fulfill the verification requirements of the newest SoC designs, as Aldec provides EDA solutions at every stage of development. Users can leverage the latest Xilinx ISE and Vivado design suites to simulate and verify designs in Aldec Active-HDL and Riviera-PRO, or incorporate Aldec FPGA-based prototyping boards utilizing Virtex-7 FPGAs for hardware emulation and SoC prototyping.

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