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Posts Tagged ‘verification’

‘Don’t Be Afraid of UVM’ Webinar on YouTube

Tuesday, October 27th, 2015

uvm_img_102715Just in time for Halloween, Aldec has released a popular past webinar Don’t be Afraid of UVM for Hardware Designers on YouTube.

Designers are usually very busy doing their work and have little time left for experimentation with new methodologies. Unfortunately for them, official documentation of UVM (Universal Verification Methodology) was written by Verification Engineers for Verification Engineers, concentrating on high-level features and completely neglecting lower-level details such as connecting UVM testbench to your design.

Our webinar starts with solid review of SystemVerilog interfaces with special attention paid to Virtual Interfaces. Then it proceeds to Sequences and other Data Items, processed by Sequencers and fed to the design under test via Drivers. The role of Monitors and Scoreboards in analysis of results is explained. The presentation concludes with environment configuration and running test from the top-level module.

For the rest of this article, visit the Aldec Design and Verification Blog.

Emulation: Thinking outside of the Big Box

Tuesday, September 22nd, 2015
 
fpga_base_emulation_bIndependent FPGA Consultant, Doug Amos, has been working in programmable logic and FPGA for over 30 years. He did his first programmable logic design in the mid-80’s (around the time Aldec was born), and since then has designed or supported countless FPGA and ASIC designs.
We’ve been pleased to work with Doug over the past several months, to help tell the story of Aldec’s advanced hardware emulation and SoC and ASIC prototyping solutions. Here is a excerpt from Doug’s recent guest blog:

There’s no question; verification is a massive time drain in SoC and other chip design projects. For many years, those with deep enough pockets have turned to so-called “Big Box” emulators in order to recover some of the time lost on RTL simulation, but what about the rest of us? Is there another way to accelerate verification and reduce our overall project schedule? Yes there is; and at Aldec they call it FPGA-based Emulation.

“FPGAs; aren’t they just for prototyping?”

Sure, FPGAs are the fastest platform for prototyping, but we can also harness that speed into our verification environment, then we can achieve runtime performance 2x to 5x faster than traditional “big box” emulation systems, and all at a fraction of the cost per gate per MHz. The most significant differences between FPGA usage in prototypes and in emulation is shown in table 1.

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So, what does a vendor-independent simulator look like?

Friday, May 15th, 2015

blog_independent_simulator_051515Well, the short answer to that is, “Awesome”. Perhaps, as the product manager of a simulation tool, I’m a little biased. Not to discount the challenges that FPGA design teams face on daily basis, particularly with device complexities now going through the roof.

There was a time, not so long ago, when using a single FPGA device from one vendor was not so uncommon and simulation and verification were quite interchangeable terms. However in recent years, with the development of more complex FPGAs and an even more complex design process involving the use of IPs, VIPs and third party models , the need for vendor agnostic tools for simulation and verification has become more evident.

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How HES™ Technology Solved Problems for These Users

Monday, October 20th, 2014

HES_USE_CASESRecognizing a problem that engineers are facing and developing a solution has been Aldec’s rather straight-forward mantra for going on thirty years now. Aldec launched its Hardware Emulation Solutions (HES) product in 2003, integrating RTL simulation with hardware emulation, and offering hardware and software design teams the ability to work concurrently. Today HES™ is a fully automated and scriptable HybridVerification and Validation environment for SoC and ASIC designs capable of bit-level simulation acceleration, SCE-MI 2.1 transaction emulation, hardware prototyping, and virtual modeling.

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Stress-Relief for Requirements-Based Verification

Wednesday, July 16th, 2014

DO-254-RequirementsIf they’re being honest, anyone who has verified an FPGA under strict DO-254 guidance will tell you that it is stressful. Show me an engineer on their first DO-254 project – and I’ll show you someone pulling out their hair and downing what is probably their 5th cup of coffee while these important questions weigh heavy on their minds:

Have we reviewed all FPGA requirements and validated derived FPGA requirements? Do we have a good record of the review activities?

Do I have a test for each functional FPGA requirement? What’s the status of the tests? How do I track the progress and document the results?

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DO-254/CTS™ solves Elbit’s major challenges

Tuesday, June 24th, 2014

Blog_img_062414Aldec has been working closely with Elbit Systems in Israel on an important DO-254 project for some time now. Using Aldec’s specialized solution DO-254/CTS™ as their primary FPGA physical testing platform, Elbit recently passed a critical EASA verification audit for DO-254/ED-80 DAL A FPGAs.

As a DO-254 evangelist, I have long recognized the value and benefits of Aldec’s solution to the avionics industry, so it was particularly rewarding to hear these words from Moshe Porian, Logic Design Verification Group Leader at Elbit Systems Aerospace Division, “Aldec helped us solve several of our verification challenges. This is the first time in Elbit’s history that we have been able to bring more than 5 FPGA devices to the audit.”

DO-254/CTS solved Elbit’s major challenges, enabling them to test in hardware 100% of FPGA pin-level requirements. As opposed to developing software test vectors, Elbit used their simulation testbench as test vectors for FPGA at-speed testing which cut their development costs. For the rest of this article, visit the Aldec Design and Verification Blog.

The 80s music at DAC was my idea. You’re welcome.

Tuesday, June 24th, 2014

If you attended the Monday Night Reception at DAC 2014, you were greeted with a blast of 80s pop music. If you then said to yourself, “I’d like to meet the genius behind that idea” – that would be me. A few weeks before DAC, our marketing manager came to me with the task of being the DJ for the Monday night reception. As soon as I heard “DJ” I envisioned turntables, cool headphones, disco lights and all the fame that follows. My dreams were dashed a few moments later when she explained that I would only have a PA and a laptop.

Undaunted, I resolved to be the best DJ in the history of DAC Monday Night Networking Receptions. The first challenge was finding music everyone would enjoy. I naturally settled on 80s pop as my genre. I had the brilliant idea of picking a few songs from each year and playing it as a progressive 80s timeline during the evening. I changed my mind when I realized that bright idea would require some serious manual research and work.

Did I give up? Of course not. I did what any good engineer would do – I found an easy (and smart) solution that did not require substantial extra effort – a bit like re-using verification ip’s instead of making them from scratch. This level of engineering genius is often mistakenly perceived as laziness, but I like to call it being smart. In fact I recently wrote a blog on the topic of working smart not hard.

For the rest of this article, visit the Aldec Design and Verification Blog.

OS-VVM CoveragePkg, A Detailed Example

Thursday, May 15th, 2014

Alex Grove, FirstEDA Applications Specialist, was kind enough to author a guest blog for Aldec. Here’s an excerpt:

Here in Europe, I recently had the opportunity to work with Jim Lewis, OS-VVM Chief Architect and IEEE 1076 Working Group Chair, on the first Advanced VHDL Testbenches & Verification training course. This training, held in Bracknell, UK, was attended by engineers from several major European system companies who design and verify programmable devices (FPGAs). VHDL is by far the dominate language used by Europe’s system companies for the design and verification of FPGAs, however it is unclear to many how to enhance their verification with VHDL. What I have found is that experienced FPGA design engineers (including myself) are not utilising the VHDL language for verification.

Jim Lewis introduces VHDL’s verification capabilities, including new VHDL 2008 features and the Open Source VHDL Verification Methodology (OSVVM). OSVVM provides a methodology for testbench development and verification packages that provide functional coverage and random value generation. (more…)

See the Future with Impact Analysis

Wednesday, April 9th, 2014

Imagine if you could look into the future…

–   See the impact of requirements changes before they occur.

–   Know with certainty which lines of code in an HDL design or testbench file needed to be re-evaluated based on a change request.

–   Understand how a requirement change impacts the project schedule to help plan and allocate resources effectively.

Impact Analysis Defined

Seeing the future is possible with Impact Analysis, a practice within the change control process of product development. Impact Analysis provides information on what design and verification elements, artifacts, hardware components and materials, personnel, assets or activities that may be affected due to a requirement change. Armed with Impact Analysis data, you can then determine which elements to re-evaluate, modify, and even re-create if necessary.

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Simulate Smarter than a Secret Agent

Thursday, March 13th, 2014

In James Bond movies, Agent 007 has some awesome gadgets but never listens to Q’s instruction on how to use them properly. I’ve often wondered what it would be like if Bond actually did learn about the various features of his tools and how to use them most efficiently.

Sure, that would probably eliminate all of the plot twists that make for a great movie, but when it comes to real life – I don’t care for plot twists. What about you? If you were a secret agent given these tools to keep you out of trouble or even save your life – would you take the time to learn about all of the features?

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S2C: FPGA Base prototyping- Download white paper



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