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Posts Tagged ‘IP’

Why I see C in SCE-MI

Friday, March 18th, 2016

blog_img_scemi_022416The two questions I hear most often while doing presentations about SCE-MI transaction based emulation are “Can we have coffee break?” and “Why do we need a thin C layer between two SystemVerilog tops”?

You a probably reading this during a coffee break, so let’s jump to second question. It refers to this diagram showing how to connect a SystemVerilog testbench (usually UVM) with DUT in SystemVerilog using a DPI transactor, as defined by the Function-based.




S2C: FPGA Base prototyping- Download white paper

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