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Posts Tagged ‘FPGA’

DO-254: Insights from a DER

Wednesday, June 26th, 2013

An Interview with FAA Consultant DER, Randall Fulton

A few weeks ago I had the opportunity to sit down with an avionics industry certification expert, FAA Consultant Designated Engineering Representative (DER), Randall Fulton. We began discussing common mistakes in DO-254 projects, and then branched out to many different areas including future of DO-254, industry engineering best practices, and his advice to organizations new to DO-254.


Louie: In your experience, what are the common mistakes in DO-254 projects?

Randall: Starting certification liaison activities and the SOI-1 planning audit after the design already exists.  Many projects also need to read the additional guidance from the FAA in Order 8110.105 to understand the impact and be prepared to show the data to satisfy the Order. Organizations also underestimate the resources required for a project. This includes staffing as well as managing all the data. Another common area is not appreciating the impact of effective requirements writing skills.


Demystifying Traceability

Monday, June 17th, 2013

For DO-254 Compliant FPGAs and ASICs

I have been getting a lot of questions from our customers about traceability in the context of DO-254 and airborne FPGAs and ASICs.  It seems that there are several new concepts and terminologies associated to traceability that are new to most of us.  So I thought I would shed some light in this blog and explain the basic 5 terminologies. Also I have always liked the word “demystify”, but never had the chance to use it – so here is my chance.

Traceability – Traceability is the activity that maps all of the design and verification elements back to requirements to ensure that what is being built and tested is based on the requirements. Traceability is the correlation between system requirements, FPGA requirements, conceptual design, HDL design, post-layout design, verification test cases, testbench and test results.

Downstream Traceability – A top to bottom reporting activity that shows the mapping or correlation between system requirements, FPGA requirements, HDL design, test case, testbench and test results.  Running a downstream traceability can expose FPGA requirements that are not implemented by any HDL function or not covered by a test case.

Upstream Traceability – A bottom to top reporting activity that shows the mapping or correlation between test results, testbench, test case, HDL design, FPGA requirements and system requirements.  Running an upstream traceability can expose derived FPGA requirements or unused HDL functions.  Tools like Spec-TRACER can also use upstream traceability to expose all of the design and verification elements associated to a FAILED simulation result.


‘Wireless Algorithm Validation’ with Aldec and Agilent

Thursday, May 30th, 2013

Free DAC INSIGHT Presentation

Free DAC INSIGHT PresentationAt the fast-approaching Design Automation Conference (DAC) 2013 in Austin, TX, Aldec will co-host an INSIGHT Session with Agilent Technologies on how to validate a digital signal processing algorithm for both floating and fixed point levels. As Riviera-PRO Product Manager, I will join Agilent Senior Product Marketing Engineer FAE, Sangkyo Shin, on Wednesday, June 5th at 2pm in presenting a combined Agilent/Aldec FPGA flow that can be used to quickly validate communications digital signal processing (DSP) algorithms and accelerate physical layer (PHY) performance measurements.


Mr. Shin will review the system-level design challenges and how to solve them using the SystemVue™ software, which provides the capabilities needed to evaluate and design modern communication systems and related products. I will then take the auto-generated HDL code from a system-level concept down to HDL simulation in Aldec Riviera-PRO™ and FPGA implementation on Aldec HES-5™ hardware prototyping board. Attendees will gain valuable insight on the cross-domain approach to traditional FPGA design flow and learn how to validate FPGA design for leading edge wireless and radar system with a system-level simulation tool integrated into the traditional hardware design flow.


Industry’s first Requirements Lifecycle Management for Safety-critical FPGAs and ASICs

Monday, May 20th, 2013

With the explosion of both in size and complexity of today’s FPGAs and ASICs, methodologies to efficiently manage and control requirements from concept to product rollout have never been more crucial to produce high quality and reliability products on time and within budget.  Developers of FPGAs and ASICs used for safety-critical applications face even greater challenges because of the strict requirements-based development process they have to follow to achieve industry compliance.

How do we make sure that our final product safely functions as intended? How do we manage and track requirements changes effectively?  Do the developers know what requirements changed? How do we establish and maintain traceability? Have we tested all the requirements? These are real and common questions and challenges that arise during FPGA/ASIC development for safety-critical applications.


Register for Aldec Technical Sessions & Demos at DAC 2013

Thursday, May 16th, 2013

DAC2013This year’s Design Automation Conference (DAC) will be held in Austin, Texas.  If we survive the 70% humidity, our team looks forward to meeting you at Booth #2225 from June 3-5. Aldec HQ is located in Nevada just outside of Las Vegas… so we’re accustomed to more of a dry heat.

We invite you to register at to attend a technical sessions led by Aldec’s top engineers from all over the world. I can’t stress enough how important it is to pre-register since these sessions do fill up quickly. You’ll also get a free t-shirt when you attend one of our sessions – we’ve designed some pretty cool ones to give away this year.

Aldec has also teamed up with Agilent to deliver a DAC Insight Presentation on Wireless Algorithm Validation Wednesday, June 5, 2013 from 2:00-4:00pm. Learn more.


S2C: FPGA Base prototyping- Download white paper

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