Posts Tagged ‘FPGA’
Monday, May 23rd, 2016
The hardest part of DO-254 is not the requirements. It’s not the design. It’s not the verification.
We just wrapped up this year’s 3-day DO-254 Practitioner’s Course, and each year I learn something new. In this year’s training we had attendees from major aerospace companies including Curtiss Wright, Rolls Royce, Sierra Nevada Corporation, Thales and Woodward. It’s always a pleasure to meet the aerospace folks and learn about their projects, goals and challenges. This is the fifth year we’ve done these trainings and each time I pick up subtle points from the instructor showing his impressive expertise in the subject.
This year’s subtle point that I picked up is about the hardest part of DO-254.
The hardest part of DO-254 is the cultural change that needs to take place in order for the organization to successfully comply to DO-254. This can be the make or break of the project. It doesn’t matter if you have top-notch planning documents if no one will adhere to them. It doesn’t matter if you’ve written 1000+ page requirements document, but the verification engineers cannot use them because the requirements are not verifiable. It doesn’t matter if you have the best design standards if your designers would not abide by them. It doesn’t matter if you have the latest verification tools but no one in your team understands how to satisfy tool assessment and qualification. It doesn’t matter if you have the most comprehensive review checklists if your reviewers will not use them and document the review activities and results.
DO-254 is a collection of industry best practices and all of its processes are tightly integrated, but it doesn’t matter if you have the DO-254 processes tightly in place if your team members will not abide by them. The hardest part of DO-254 is the cultural change that needs to be embraced by all team members. The cultural change is what can get you.
Many organizations new to DO-254 are eager to jump on board and start applying DO-254 to their projects due to its high demand in the avionics industry. You might be ready to take the leap and make the cultural change yourself, but is the rest of your team and organization ready for the cultural change?
If you’d like to learn more, or register for next year’s class, call us at 1+702-990-4400 or email firstname.lastname@example.org.
For the rest of this article, visit the Aldec Design and Verification Blog.
Monday, May 23rd, 2016
Recently I read a Semiwiki article, Army of Engineers on Site Only Masks Weakness, in which author Jean-Marie Brunet of Mentor Graphics wrote that FPGA Prototyping requires an army of tech support engineers on-site to mask the weaknesses of FPGA prototyping flows. As the Tech Support Manager for Aldec Hardware Emulation Solutions, I have to admit I’ve never had to deploy an army onsite.
It is true that FPGA Prototyping is more challenging than emulation. Yet, for the time invested in prototype setup, developers are rewarded with a validation platform that is capable of running orders of magnitude faster than emulation.
Tuesday, December 15th, 2015
FPGA designers using VHDL have three choices: Stick with VHDL, switch to SystemVerilog, or.. use the best of both. This guest blog from Doug Perry, Senior Member Technical Staff at Doulos, outlines the pros and cons of each.
The latest crop of FPGA devices are enormous when compared to ASICs that were built not that long ago. Verifying these ASICs required detailed plans, multiple tools, and sometimes special languages. Verification was key because the cost of a respin was prohibitive. FPGA designers using VHDL have three choices: Stick with VHDL, switch to SystemVerilog, or.. use the best of both. This guest blog from Doug Perry, Senior Member Technical Staff at Doulos, outlines the pros and cons of each.
The same is not necessarily true of FPGAs because they can simply be re-programmed when an error is found. However the cost of finding the error in the lab can still be very expensive. This is related to the fact that the number of LUTs available in the device has skyrocketed, but the number of IO pins has not. Therefore getting visibility into the inner workings of the device from outside becomes much more difficult. Finding the source of an error therefore also becomes increasingly difficult. To counteract this problem, designers need to find errors before the device gets into the lab. To do this they need to adopt ASIC-like verification methodologies.
Tuesday, September 8th, 2015
Friday, May 15th, 2015
Well, the short answer to that is, “Awesome”. Perhaps, as the product manager of a simulation tool, I’m a little biased. Not to discount the challenges that FPGA design teams face on daily basis, particularly with device complexities now going through the roof.
There was a time, not so long ago, when using a single FPGA device from one vendor was not so uncommon and simulation and verification were quite interchangeable terms. However in recent years, with the development of more complex FPGAs and an even more complex design process involving the use of IPs, VIPs and third party models , the need for vendor agnostic tools for simulation and verification has become more evident.
Wednesday, July 30th, 2014
I am a Hardware Technical Support Manager. Ask Me Anything!
Earlier this summer, I joined a team traveling from Aldec’s R&D offices in Kraków, Poland to attend the annual Design Automation Conference (DAC) in San Francisco. As Technical Support Manager for Aldec’s Hardware Products Division, my goals for this event were two-fold. First, as we’ve made huge enhancements to our HES-7™ FPGA prototyping solution in the past year, I wanted to be there in person to share more about them in demos and presentations at the Aldec booth.
Secondly, and really my favorite part of DAC, I wanted to hear from engineers in the field looking for solutions to their real-world problems. Sometimes I have immediate answers for their questions, like the engineer who was not happy with their current solution’s implementation time or the fellow that needed support for in-house development boards. Occasionally though, I don’t have an immediate answer and instead they’ve given me valuable ideas that I get to take back home to my team so we can set to work developing solutions.
Wednesday, July 16th, 2014
If they’re being honest, anyone who has verified an FPGA under strict DO-254 guidance will tell you that it is stressful. Show me an engineer on their first DO-254 project – and I’ll show you someone pulling out their hair and downing what is probably their 5th cup of coffee while these important questions weigh heavy on their minds:
Have we reviewed all FPGA requirements and validated derived FPGA requirements? Do we have a good record of the review activities?
Do I have a test for each functional FPGA requirement? What’s the status of the tests? How do I track the progress and document the results?
Tuesday, June 24th, 2014
Aldec has been working closely with Elbit Systems in Israel on an important DO-254 project for some time now. Using Aldec’s specialized solution DO-254/CTS™ as their primary FPGA physical testing platform, Elbit recently passed a critical EASA verification audit for DO-254/ED-80 DAL A FPGAs.
As a DO-254 evangelist, I have long recognized the value and benefits of Aldec’s solution to the avionics industry, so it was particularly rewarding to hear these words from Moshe Porian, Logic Design Verification Group Leader at Elbit Systems Aerospace Division, “Aldec helped us solve several of our verification challenges. This is the first time in Elbit’s history that we have been able to bring more than 5 FPGA devices to the audit.”
DO-254/CTS solved Elbit’s major challenges, enabling them to test in hardware 100% of FPGA pin-level requirements. As opposed to developing software test vectors, Elbit used their simulation testbench as test vectors for FPGA at-speed testing which cut their development costs. For the rest of this article, visit the Aldec Design and Verification Blog.