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Posts Tagged ‘aviation’

Aldec Springs Into Action: A look back at a busy show season

Thursday, April 6th, 2017

Aldec at DVConIt’s been a busy season for Aldec. The weather has warmed here in the desert and as the trees and greenery enliven in spring, Aldec has also been bursting with activity. From DVCon to the International Symposium on FPGAs in the US to Embedded World and CTIC in Europe, there have been some exciting developments from Aldec in verification, embedded systems, and DO-254.

These major events and conferences have been a great time to provide some updates on the latest Aldec endeavors and to provide an in-person look at the capability of our tools.

The DVCon U.S. Conference and Exhibition held in San Jose, California, holds a special place in my heart because it was the first industry conference I attended after starting my career in EDA. Every year I enjoy returning in order to see the latest verification advancements and to speak with those who are hard at work trying to improve verification efforts. Portable stimulus was a hot topic and it seemed like emulation was growing in popularity. This year we brought our Hardware Emulation Solutions (HES™) so that people could get an in-person look at our hardware. We showed off the speed benefits of emulation over traditional simulation by hooking up a UVM testbench to an in-house network-on-chip design running in our FPGA boards. As design sizes increase, I think emulation will become a more widely adopted solution to the simulation bottleneck.

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Stress-Relief for Requirements-Based Verification

Wednesday, July 16th, 2014

DO-254-RequirementsIf they’re being honest, anyone who has verified an FPGA under strict DO-254 guidance will tell you that it is stressful. Show me an engineer on their first DO-254 project – and I’ll show you someone pulling out their hair and downing what is probably their 5th cup of coffee while these important questions weigh heavy on their minds:

Have we reviewed all FPGA requirements and validated derived FPGA requirements? Do we have a good record of the review activities?

Do I have a test for each functional FPGA requirement? What’s the status of the tests? How do I track the progress and document the results?

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Does DO-254/CTS™ Support FPGAs with Serial High-speed I/Os?

Wednesday, November 20th, 2013

As a DO-254 evangelist, I travel quite a bit attending conferences and meeting customers all over the world. One question I occasionally get from engineers is whether Aldec’s mil/aero verification solution, DO-254/CTS™, supports verification of FPGA designs with high speed interfaces (for example ARINC 818, LVDS, DDR3 or PCIe).

Depending where I’m at I’ll tell them, “Oui!” or “Hai!” or simply “You bet it does”. Occasionally I’ll respond, “화장실이 어디 있어요!” in hopes that someone will kindly direct me to the nearest restroom.

For the rest of this article, visit the Aldec Design and Verification Blog.




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