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Posts Tagged ‘ARM’

Introduction to AXI Protocol: Understanding the AXI interface

Wednesday, August 17th, 2016

Introduction-to-AXI-ProtocolToday’s article is authored by Brandon Wade, Aldec FAE Intern. Brandon is currently working on his B.S. in computer engineering from the University of Nevada, Las Vegas and is set to graduate in 2017. His interests include processor architectures, and the logic of these hardware designs. As a field application engineer intern, Brandon has worked extensively with Aldec’s own simulation software such as Active-HDL and Riviera-PRO. 

When part of a team, your group can become more capable than a single individual, but only if your team can work together and communicate effectively. Having members of a group talk over each other leads to nothing but a cacophony, and nothing gets done. For this reason protocols need to be established, such as letting others speak without interruption, or facing those you are addressing. The same is necessary with electronics, especially with system on chip (SoC) designs.

The protocol used by many SoC today is AXI, or Advanced eXtensible Interface, and is part of the ARM Advanced Microcontroller Bus Architecture (AMBA) specification. It is especially prevalent in Xilinx’s Zynq devices, providing the interface between the processing system and programmable logic sections of the chip.

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Emulation: Thinking outside of the Big Box

Tuesday, September 22nd, 2015
 
fpga_base_emulation_bIndependent FPGA Consultant, Doug Amos, has been working in programmable logic and FPGA for over 30 years. He did his first programmable logic design in the mid-80’s (around the time Aldec was born), and since then has designed or supported countless FPGA and ASIC designs.
We’ve been pleased to work with Doug over the past several months, to help tell the story of Aldec’s advanced hardware emulation and SoC and ASIC prototyping solutions. Here is a excerpt from Doug’s recent guest blog:

There’s no question; verification is a massive time drain in SoC and other chip design projects. For many years, those with deep enough pockets have turned to so-called “Big Box” emulators in order to recover some of the time lost on RTL simulation, but what about the rest of us? Is there another way to accelerate verification and reduce our overall project schedule? Yes there is; and at Aldec they call it FPGA-based Emulation.

“FPGAs; aren’t they just for prototyping?”

Sure, FPGAs are the fastest platform for prototyping, but we can also harness that speed into our verification environment, then we can achieve runtime performance 2x to 5x faster than traditional “big box” emulation systems, and all at a fraction of the cost per gate per MHz. The most significant differences between FPGA usage in prototypes and in emulation is shown in table 1.

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Biggest Hits and Trends from ARM TechCon

Wednesday, November 6th, 2013

The recent ARM® TechCon Conference in Santa Clara was definitely the front-runner of my favorite conferences that I attended this year. Fun, informative and filled with software engineers, physical designers, design verification teams, and hardware engineers – ARM TechCon was the place to be to learn about the latest innovations from the embedded industry. Aldec was there showcasing our HES-DVM™ and HES-7™ platforms, which enable engineers to utilize emulation and FPGA-based prototyping to verify the latest ARM designs.

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