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Louie De Luna
Louie De Luna
Louie is responsible for FPGA level in-target testing technology and requirements lifecycle management for DO-254 and other safety-critical industry standards. He received his B.S. in Computer Engineering from University of Nevada in 2001. His practical engineering experience includes areas in … More »

Following the Roadmap to Successful Traceability

 
September 23rd, 2013 by Louie De Luna

If DO-254 is both the mission and the map required to achieve compliance, then traceability represents the roads on that map. Consider this.

- Roads connect two or more places on a map; traceability connects two or more elements in a project (such as functions, requirements, concept, design, verification data and test results).

- Road names help identify specific places that are linked to it; traceability names help identify specific project elements that are linked to it.

– In the absence of roads, reaching your destination is practically impossible;  in the absence of traceability achieving compliance is also practically impossible.

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SCE-MI for SoC Verification

 
September 18th, 2013 by Bill Jason

Today’s System-on-Chip verification teams are moving up in the levels of abstraction to increase the degree of coverage in the system design. As designs grow larger, we start to see an increase in test time within our HDL simulations. Engineers can utilize Hardware-Assisted approaches such as simulation acceleration, transaction-level co-emulation, and prototyping to combat the growing simulation times of an RTL simulator. In this article, we’ll dive much deeper into the transaction-level co-emulation methodology.

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Verilog-AMS & Multi-Level Simulation

 
September 16th, 2013 by Dmitry Melnik

It occurred to me that it has been a few months since we shared an update on HiPer Simulation A/MS. Following DAC 2013 and Daniel Payne’s posts at SemiWiki (post 1, post 2), we at Aldec and Tanner EDA have received many inquiries from the field, conducted a number of evaluations, and deployed our analog/mixed-signal (AMS) design flow with our first mutual customers. In this article, I’ll share more the mixed-signal simulation methodology and highlight some of Verilog-AMS use cases that we have seen in the field.

Digital & Analog HDLs

The Verilog and VHDL languages were designed to handle discrete signals, where the number of possible signal values is limited (e.g. 1, 0, X, Z). Whereas Verilog-A was designed to handle continuous-time (analog) signals, that can take any value from a continuous range at any point.

For the rest of this article, visit the Aldec Design and Verification Blog.

The WHAT is mandatory but the HOW is entirely optional

 
September 9th, 2013 by Satyam Jani

You look confused. Perhaps I owe you an explanation. Anyone familiar with hardware design flow knows that it starts with specification and ends with implementation. The specification in this flow is the “What” – it defines what needs to be designed. The process for implementation is the “How” – it defines how you are going to achieve it.

Let’s break down just one part of the “How” or implementation – the Design Process. For many years hand-coded RTL has been used as the de facto method for implementation and it is still being used as predominant method for designing cutting-edge hardware. But does it follow that it is the most efficient method? I would say probably not, especially given the ever-growing complexity of the hardware.

For the rest of this article, visit the Aldec Design and Verification Blog.

90’s Kid Active-HDL Celebrates Sweet 16

 
August 28th, 2013 by Satyam Jani

As the proud Product Manager of Aldec’s  FPGA Design Simulation solution,  I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997. Active-HDL has not merely stood the test of time, it has dominated the FPGA market like a Hulk Hogan smackdown with powerful simulation performance and debugging tools.

The key to Active-HDL’s long-term success lies in Aldec’s customer-centric philosophy. Simply put, we really do listen closely to our users and invest heavily in our tools. For this reason, continued simulation performance optimizations from release to release enable users to benefit from Active-HDL’s faster simulation even as the size of FPGA designs continues to grow.

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The Magic of CyberWorkBench

 
August 22nd, 2013 by Satyam Jani

Dr. Benjamin Carrion Schafer, Assistant Professor at Hong Kong Polytechnic University (and longtime fan of Aldec’s latest offering, CyberworkBench from NEC) was kind enough to author a guest blog for Aldec. Here’s an excerpt:

My first encounter with NEC’s CyberWorkBench (CWB) was in 2003 while attending DAC. Like most people, I was surprised to see a big Japanese company offering EDA tools. NEC is definitely known more for its consumer products and telecommunication equipment. I have to admit, the main reason I stopped at their booth – was that they had hired a magician.

This magician told the audience he would teach us a trick and give us a set of magic cards if we stayed until the end of the presentation. I did and I received my set of magic cards (which I still keep). At the same time I also became a CWB user and even wound up working for NEC.

As an assistant Professor at the Hong Kong Polytechnic University, I currently teach advanced VLSI courses and use CWB. It has some amazing capabilities. Let’s start with the fact that it supports ANSI-C and SystemC. Although SystemC might be a step in the right direction to have a unique standardized IEEE language, supported by all main HLS tools, it is not very intuitive and takes some time to master (especially if the user does not have a C++ background). Here is where ANSI-C support becomes very handy. Most people do know ANSI-C and it is very straightforward to convert any ANSI-C SW description into synthesizable C code.

For the rest of this article, visit the Aldec Design and Verification Blog.

HW Designers: Brush up on your SV with Online Training

 
August 12th, 2013 by Jerry Kaczynski

Fast Track to SystemVerilog for Verilog Users

The ability to adopt methodologies and get up to speed quickly is critical in today’s fast moving environment. Aldec offers Fast Track™ ONLINE trainings designed for busy engineers to increase their productivity and enhance their skill level from the comfort of their own browser.

Got SystemVerilog? While it may be a fashionable topic among verification engineers, it’s generally a shunned subject among hardware designers. While there are many good reasons for this (overgrown size of the SystemVerilog standard, expensive options required to use many language features in simulation, poor support in low-end tools, etc.), designers familiar with classical Verilog can benefit greatly from the features available in the Design Subset of SystemVerilog. Designing state machines is one excellent example. It is as easy and elegant in SystemVerilog as it is in VHDL – and those machines even synthesize in better tools!

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Legacy Schematic Designs Giving you a Headache?

 
July 30th, 2013 by Deep Shah

Retargeting Legacy Designs for New Technology

Digital design has come a long way since its inception from drawing schematic on paper, to CAD tools which can be used to draw schematics, and to today’s most popular (and efficient) process of describing designs through HDLs.

I recently encountered a customer with a legacy design developed in block diagram format. If he hadn’t been an Aldec customer, he might have been stuck. Fortunately,  Aldec Active-HDL™ provides utilities for importing legacy schematic based designs from Xilinx® Foundation Series, ViewLogic™, ViewDraw™, Active-CAD™ or any schematic tools that can output an EDIF netlist.

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Leverage Hardware Acceleration for Faster Simulation

 
July 24th, 2013 by Bill Jason

Breaking the Bottleneck of RTL Simulation

Utilizing hardware acceleration in a System-on-Chip verification cycle can speed-up HDL simulation runs from 10-100x, while providing the robust debugging available from an RTL simulator. Acceleration (also referred to as Co-Simulation) combines the speed of FPGA-based prototyping boards, by offloading resource hungry modules into the FPGA, while non-synthesizable constructs of the testbench remain in the RTL simulator.

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Working Smarter not Harder

 
July 22nd, 2013 by Sunil Sahoo

To Accelerate DSP Design Development

If we’re being honest, human beings, especially engineers, are lazy. Let’s face it, most inventions ever made were created for the sole purpose of making our lives easier. The same goes for the manner in which we create our designs. In the not so distant past, engineers were drawing designs by hand on huge trace paper, placing them one below the other to form layers. This sounds like hard work to me! The lazy me would have wanted a smart (read: easy) solution to this process. Then along comes the EDA industry, which Aldec has been part of since 1984, making it much easier for us to do our designs.

Some might argue that EDA was born out not out of laziness, but in fact neccessity, due to increasing design complexity. True, it is impossible to imagine how the pencil and paper method could even work today. The point is it didn’t, and we now have automated the process to such an extent all you need do is enter some parameters in a tool wizard.

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