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 Aldec Design and Verification
Louie De Luna
Louie De Luna
Louie is responsible for FPGA level in-target testing technology and requirements lifecycle management for DO-254 and other safety-critical industry standards. He received his B.S. in Computer Engineering from University of Nevada in 2001. His practical engineering experience includes areas in … More »

Stress-Relief for Requirements-Based Verification

 
July 16th, 2014 by Louie De Luna

DO-254-RequirementsIf they’re being honest, anyone who has verified an FPGA under strict DO-254 guidance will tell you that it is stressful. Show me an engineer on their first DO-254 project – and I’ll show you someone pulling out their hair and downing what is probably their 5th cup of coffee while these important questions weigh heavy on their minds:

Have we reviewed all FPGA requirements and validated derived FPGA requirements? Do we have a good record of the review activities?

Do I have a test for each functional FPGA requirement? What’s the status of the tests? How do I track the progress and document the results?

Read the rest of Stress-Relief for Requirements-Based Verification

DO-254/CTS™ solves Elbit’s major challenges

 
June 24th, 2014 by Louie De Luna

Blog_img_062414Aldec has been working closely with Elbit Systems in Israel on an important DO-254 project for some time now. Using Aldec’s specialized solution DO-254/CTS™ as their primary FPGA physical testing platform, Elbit recently passed a critical EASA verification audit for DO-254/ED-80 DAL A FPGAs.

As a DO-254 evangelist, I have long recognized the value and benefits of Aldec’s solution to the avionics industry, so it was particularly rewarding to hear these words from Moshe Porian, Logic Design Verification Group Leader at Elbit Systems Aerospace Division, “Aldec helped us solve several of our verification challenges. This is the first time in Elbit’s history that we have been able to bring more than 5 FPGA devices to the audit.”

DO-254/CTS solved Elbit’s major challenges, enabling them to test in hardware 100% of FPGA pin-level requirements. As opposed to developing software test vectors, Elbit used their simulation testbench as test vectors for FPGA at-speed testing which cut their development costs. For the rest of this article, visit the Aldec Design and Verification Blog.

The 80s music at DAC was my idea. You’re welcome.

 
June 24th, 2014 by Sunil Sahoo

If you attended the Monday Night Reception at DAC 2014, you were greeted with a blast of 80s pop music. If you then said to yourself, “I’d like to meet the genius behind that idea” – that would be me. A few weeks before DAC, our marketing manager came to me with the task of being the DJ for the Monday night reception. As soon as I heard “DJ” I envisioned turntables, cool headphones, disco lights and all the fame that follows. My dreams were dashed a few moments later when she explained that I would only have a PA and a laptop.

Undaunted, I resolved to be the best DJ in the history of DAC Monday Night Networking Receptions. The first challenge was finding music everyone would enjoy. I naturally settled on 80s pop as my genre. I had the brilliant idea of picking a few songs from each year and playing it as a progressive 80s timeline during the evening. I changed my mind when I realized that bright idea would require some serious manual research and work.

Did I give up? Of course not. I did what any good engineer would do – I found an easy (and smart) solution that did not require substantial extra effort – a bit like re-using verification ip’s instead of making them from scratch. This level of engineering genius is often mistakenly perceived as laziness, but I like to call it being smart. In fact I recently wrote a blog on the topic of working smart not hard.

For the rest of this article, visit the Aldec Design and Verification Blog.

OS-VVM CoveragePkg, A Detailed Example

 
May 15th, 2014 by Satyam Jani

Alex Grove, FirstEDA Applications Specialist, was kind enough to author a guest blog for Aldec. Here’s an excerpt:

Here in Europe, I recently had the opportunity to work with Jim Lewis, OS-VVM Chief Architect and IEEE 1076 Working Group Chair, on the first Advanced VHDL Testbenches & Verification training course. This training, held in Bracknell, UK, was attended by engineers from several major European system companies who design and verify programmable devices (FPGAs). VHDL is by far the dominate language used by Europe’s system companies for the design and verification of FPGAs, however it is unclear to many how to enhance their verification with VHDL. What I have found is that experienced FPGA design engineers (including myself) are not utilising the VHDL language for verification.

Jim Lewis introduces VHDL’s verification capabilities, including new VHDL 2008 features and the Open Source VHDL Verification Methodology (OSVVM). OSVVM provides a methodology for testbench development and verification packages that provide functional coverage and random value generation. Read the rest of OS-VVM CoveragePkg, A Detailed Example

See the Future with Impact Analysis

 
April 9th, 2014 by Louie De Luna

Imagine if you could look into the future…

–   See the impact of requirements changes before they occur.

–   Know with certainty which lines of code in an HDL design or testbench file needed to be re-evaluated based on a change request.

–   Understand how a requirement change impacts the project schedule to help plan and allocate resources effectively.

Impact Analysis Defined

Seeing the future is possible with Impact Analysis, a practice within the change control process of product development. Impact Analysis provides information on what design and verification elements, artifacts, hardware components and materials, personnel, assets or activities that may be affected due to a requirement change. Armed with Impact Analysis data, you can then determine which elements to re-evaluate, modify, and even re-create if necessary.

Read the rest of See the Future with Impact Analysis

Simulate Smarter than a Secret Agent

 
March 13th, 2014 by Sunil Sahoo

In James Bond movies, Agent 007 has some awesome gadgets but never listens to Q’s instruction on how to use them properly. I’ve often wondered what it would be like if Bond actually did learn about the various features of his tools and how to use them most efficiently.

Sure, that would probably eliminate all of the plot twists that make for a great movie, but when it comes to real life – I don’t care for plot twists. What about you? If you were a secret agent given these tools to keep you out of trouble or even save your life – would you take the time to learn about all of the features?

Read the rest of Simulate Smarter than a Secret Agent

For DO-254 Compliance, Hardware Flies Not Simulations

 
February 20th, 2014 by Louie De Luna

DO-254 defines 3 types of verification methods: Analysis, Test and Review. In order to satisfy the verification objectives defined in DO-254, applicants must formulate a requirements-based verification plan that employs a combination of the three methods.

Analysis vs. Test

A computerized simulation of the hardware item is considered an Analysis. Test is a method that confirms the actual hardware item correctly responds to a series of stimuli. Any inability to verify specific requirements by Test on the device itself must be justified and alternative means of verification must be provided. In DO-254, the hardware test is far more important than the simulation. Certification authorities favor verification by test for official verification credits because of the simple fact that hardware flies, not simulation models.  Requirements describing pin-level behavior of the device must be verified by hardware test.

Read the rest of For DO-254 Compliance, Hardware Flies Not Simulations

Still managing FPGA requirements with Word and Excel?

 
January 21st, 2014 by Louie De Luna

Smart engineers work smart by using tools that are readily available and that they know how to use.  Wise engineers work wisely by first evaluating the options, analyzing the results and making a strategic decision not only for the current project  but, more importantly, for upcoming projects as well.

Recently, a customer developing avionics systems came to us with their frustrations in managing FPGA requirements.  They managed higher level requirements, such as line replaceable unit (LRU) and circuit card assembly (CCA) requirements, in IBM DOORS. The FPGA requirements, test cases and their traceability to HDL design, testbench and simulation results were managed using Word and Excel.  Since DOORS lacked the capability to trace to FPGA design and verification elements necessary for DO-254 compliance, the customer felt they had to choose Word and Excel.

Why? Because Word and Excel are readily available and the team members already know how to use them.  But as their projects grew in complexity increasing the number of requirements to be managed, they found that Word and Excel have many shortcomings and realized that they are not the right tool when it comes to requirements management and traceability.

For the rest of this article, visit the Aldec Design and Verification Blog.

Much has changed in the last 30 years

 
January 10th, 2014 by Dr. Stanley M. Hyduke

When I first launched Aldec in 1984, home computers hadn’t quite taken off and innovations such as the compact disk and those oversized, power draining cellphones were still struggling to obtain mass acceptance.

Fast forward 30 years, even those of us in the electronics industry have whiplash from the speed at which technology is advancing and delivering new products. Buyers are more eager to become early adopters of innovative new technology, and smarter, faster tools are required to keep pace.

As a long-time member of the Electronic Design Automation (EDA) community, Aldec has had a front row seat to the technology race and over the years we have celebrated many successes of our own. Here, our product managers reflect on some of our most memorable highlights from 2013.

Read the rest of Much has changed in the last 30 years

It’s no accident that Aldec offers the best VHDL-2008 support

 
December 11th, 2013 by Satyam Jani

Here at the Aldec corporate office, we have a sign that reminds us all of our mission in the field of Technology. It reads, ‘To deliver solutions that provide the highest productivity to value ratio; supporting our existing products while delivering innovation to current and new technologies’. We have similar statements to reaffirm our commitment in the areas of Research, Alliances, and Culture – we call it our “Aldec DNA”.

Because we genuinely want to have a clear understanding of our user’s requirements and methodology preferences, we continually engage in surveys and interviews.  The knowledge we gain better positions us to support our existing products and to deliver that support where it matters the most to our users. If you’ve ever had that frustrating experience where your favorite tool no longer supports your methodology of choice – then you understand why this is so important.

Our Commitment to the VHDL Community

When it comes to VHDL-2008, we have learned from our customers that many are happy using the methodology – and continue to successfully deliver cutting-edge technology with it. So, while we remain committed to delivering innovation to new technologies, our R&D teams also invest a great deal of development time to ensure that Aldec solutions continue to offer a high level of support for popular languages like VHDL.

For the rest of this article, visit the Aldec Design and Verification Blog.

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