Aldec Design and Verification
Krzysztof joined Aldec in 2001 and was a key member of the team that developed HES-DVM™, Aldec's FPGA-based simulation acceleration and emulation technology. He has worked in the fields of HDL IP-core verification, testbench automation and design verification for DO-254 compliance gaining … More »
November 4th, 2015 by Krzysztof Szczur
Next week, Aldec will join other top tier organizations as a proud Silver Sponsor at DVCon Europe 2015 in Munich, Germany. There our team will offer live demonstrations of hardware-assisted verification of UVM following Doulos Ltd.’s Easier UVM guidelines. Alex Grove of Aldec will also deliver a DVCon Europe tutorial, ‘UVM Hardware Assisted Acceleration with FPGA Co-emulation’.
October 27th, 2015 by Sunil Sahoo
Just in time for Halloween, Aldec has released a popular past webinar Don’t be Afraid of UVM for Hardware Designers on YouTube.
Designers are usually very busy doing their work and have little time left for experimentation with new methodologies. Unfortunately for them, official documentation of UVM (Universal Verification Methodology) was written by Verification Engineers for Verification Engineers, concentrating on high-level features and completely neglecting lower-level details such as connecting UVM testbench to your design.
Our webinar starts with solid review of SystemVerilog interfaces with special attention paid to Virtual Interfaces. Then it proceeds to Sequences and other Data Items, processed by Sequencers and fed to the design under test via Drivers. The role of Monitors and Scoreboards in analysis of results is explained. The presentation concludes with environment configuration and running test from the top-level module.
For the rest of this article, visit the Aldec Design and Verification Blog.
September 8th, 2015 by Satyam Jani
Doulos has partnered with Aldec to deliver this Friday’s webinar, ‘Easier UVM: Helping FPGA Designers Get Started with UVM’ . Presented by Doulos CTO, John Aynsley, the 1 hour webinar includes live Q&A so it’s a great opportunity to find out how Easier UVM can work for you. The webinar includes examples from the Easier UVM Code Generator running under Aldec Riviera-PRO™.
August 25th, 2015 by Louie De Luna
You have been developing FPGAs for a long time, and you know your designs from top to bottom. You know every interface protocol, configuration and optimization. You can visualize your timing diagram like you can visualize your upcoming vacation in Hawaii. You can manually write down your memory mapping accurately while under oath. You can pinpoint all CDC paths and emulate metastability in your mind. You are confident that your designs are fault-tolerant and will function as intended. You are the master of your domain.
But… can you bet your life on it?
Are you willing to bet your life on your designs? What about the lives of the thousands of passengers sitting on the airplanes where your FPGA design is installed? How certain are you that it won’t fail in the field? If it were to fail, can it resume normal operation safely and timely? Not just MOST of the time, but EVERY time?
May 20th, 2015 by Satyam Jani
Python is making inroads in the EDA landscape, but is all the hype justified? Do the productivity benefits of a dynamic language translate to gains for real-world development for ASIC and FPGA designs? Chris Higgs of Potential Ventures will be onsite at DAC to share his experiences using Python and Aldec Riviera-PRO to take products from idea to production quickly.
Chris recently wrote a Guest Blog on the topic, visit the Aldec Design Verification Blog to learn more.
May 15th, 2015 by Satyam Jani
Well, the short answer to that is, “Awesome”. Perhaps, as the product manager of a simulation tool, I’m a little biased. Not to discount the challenges that FPGA design teams face on daily basis, particularly with device complexities now going through the roof.
There was a time, not so long ago, when using a single FPGA device from one vendor was not so uncommon and simulation and verification were quite interchangeable terms. However in recent years, with the development of more complex FPGAs and an even more complex design process involving the use of IPs, VIPs and third party models , the need for vendor agnostic tools for simulation and verification has become more evident.
April 20th, 2015 by Kamil Rymarz
How to use VIPs In Practice
Allow me to describe a typical verification process, and explain why I recommend the use of Verification IPs within the testing process.
February 24th, 2015 by Stan Hanel
Taking a cue from the open-source community, Xilinx has launched a Tcl Store that aggregates Tcl scripts contributed by the greater development community to expand the capabilities of the Vivado® Integrated Design Environment.
All Tcl scripts contributed to the Xilinx repository are free and re-distributable under an open-source license that is based on the Berkeley Source Distribution (BSD) model. Vivado users can now download apps from the Tcl Store that include practical bundles of Tcl scripts that act just like Vivado commands, including an app that can integrate Aldec Active-HDL and Riviera-PRO tools within the Vivado design flow.
To take advantage of these pre-packaged Tcl Script apps within Vivado, users can access the Tcl Store via the Vivado IDE “Tools” menu. For the rest of this article, visit the Aldec Design and Verification Blog.
February 24th, 2015 by Stan Hanel
This week, February 22-28, we celebrate National Engineers Week in the US to recognize the contributions to society that engineers make. During this time, there is added emphasis in schools on the importance of learning math, science, and technical skills.
I work with Generation STEAM, a group organized by the SYN Shop MakerSpace and the Henderson district library to create a series of STEM (Science, Technology, Engineering, [Art], and Math) classes that are free to the public. For my part, I’ve had the privilege of teaching a basic electronics class for kids a few Saturdays this year – and it’s been a blast. Our hope is that we are encouraging a few young people to follow the path of engineering.