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Stan Hanel
Stan Hanel
Stan has been active in Silicon Valley since 1979, tackling challenging opportunities such as start-up companies that attempted to apply emerging semiconductor technologies to solve engineering problems related to physical rehabilitation, robotics, and entertainment. Recently, he has joined the … More »

Scaling the “Internet of Things”

 
January 21st, 2015 by Stan Hanel

Internet-of-thingsHappy New Year!

January brought an unseasonably warm wave of weather to Las Vegas as International CES converged on the city this month.

The size and scope of this worldwide consumer electronics tradeshow continues to grow each year with new products and industries on the rise, now driven by a phenomenon called the “Internet of Things” (IoT).

Shawn Dubravac, Ph.D., Chief Economist and Director of Research for the Consumer Electronics Association (CEA) kicked off the event by presenting a summary of his new book, “Digital Destiny”.

Read the rest of Scaling the “Internet of Things”

Last call from Engineer Santa. Survey & daily drawings end Dec 12.

 
December 11th, 2014 by Engineer Santa

Well folks, last call from Engineer Santa. Aldec’s #12DaysofUsefulGifts giveaway will end this Friday, December 12 at 12pm midnight Pacific Standard Time.[preview_cut]

If you haven’t registered yet, you’ll want to hurry and visit www.aldec.com/survey. There you will take a brief verification survey and be entered to win.

If you’ve been keeping up with us on Twitter and YouTube, you know that we’ve given away some fun prizes already. If you are looking for some practical and useful gift ideas for the holidays, you might want to take a closer look. I’ve already talked about some of these from Days #1-4. We’ve given away more prizes since then and sent them to engineers all over the globe! Here, take a look…

Read the rest of Last call from Engineer Santa. Survey & daily drawings end Dec 12.

Spec-TRACER now directly integrated with IBM DOORS

 
December 10th, 2014 by Louie De Luna

Spec-TRACER-DOORS-IntegrationIn response to user feedback, Aldec has developed a direct integration between IBM® Rational ® DOORS ® and our requirements management tool, Spec-TRACER™, to enable users to extend the traceability data in DOORS to FPGA design and verification elements.

Aldec has a strong 30-year+ history of asking and listening to the engineering community and we’re proud to say, thanks to your requests, that Spec-TRACER 2014.12 featuring direct integration with DOORS… is now available to test drive.

Below you’ll find an overview of the Spec-TRACER/DOORS tool flow. DOORS remains the main source and environment for managing board requirements and other higher level requirements, while Spec-TRACER remains the main source and environment for managing FPGA requirements, conceptual design data, detailed design data, test cases, test procedures, test results, traceability data and review activities. Spec-TRACER also remains the main source for generating all the pertinent reports for the FPGA project such as requirements documents, verification procedures, test results, impact analysis reports and project status reports.

For the rest of this article, visit the Aldec Design and Verification Blog.

Looking for Practical Holiday Gift Ideas?

 
December 4th, 2014 by Engineer Santa

Happy Holidays! We’ve made it to Day 4 of Aldec’s #12DaysofUsefulGifts giveaway. If you’ve been keeping up with us on Twitter and YouTube, you know that we’ve given away some fun prizes already. But that’s just the beginning, the prizes will get larger each day until the contest ends on December 12th!

If you are looking for some practical and useful gift ideas for the holidays, take a look at some of the fun prizes we’ve already given away.

Day #1day-1_400 Day #2day-2_400
Professional Cleaning Set for DSLR Cameras

Air Vent Mount for Cell Phones

Winner! Jonathan S.

Miles Kimball Manual Hand Held Shredder

Bushnell Falcon 7×35 Binoculars with Case

Winner! Alan S.

Day #3day-3_400 Day #4day-4_400
Magisso Tea Cup

Grillight LED BBQ Spatula

Winner! Daniel H.

Sugru Hardware Sealer

Pocketmonkey Wallet Multi-Tool

Could be you! Enter today at

www.aldec.com/survey

To enter Aldec’s #12DaysOfUsefulGifts drawing, visit www.aldec.com/survey. There you will take a brief verification survey and automatically be entered to win. You only need to take the survey once to be eligible for daily drawings from Dec 1st-12th. You can also earn additional chances to win by sharing the contest link and viewing the daily contest video. Follow Aldec on Twitter where we will announce each day’s winner and unveil the next day’s prize. Good luck!

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How HES™ Technology Solved Problems for These Users

 
October 20th, 2014 by Krzysztof Szczur

HES_USE_CASESRecognizing a problem that engineers are facing and developing a solution has been Aldec’s rather straight-forward mantra for going on thirty years now. Aldec launched its Hardware Emulation Solutions (HES) product in 2003, integrating RTL simulation with hardware emulation, and offering hardware and software design teams the ability to work concurrently. Today HES™ is a fully automated and scriptable HybridVerification and Validation environment for SoC and ASIC designs capable of bit-level simulation acceleration, SCE-MI 2.1 transaction emulation, hardware prototyping, and virtual modeling.

Read the rest of How HES™ Technology Solved Problems for These Users

Averting CDC Roadblocks in FPGA Design

 
September 19th, 2014 by Ajay Pradhan

Rough-RoadThis being my first summer in Las Vegas, it is the first time I’ve experienced the rainy, desert monsoon season and the powerful flash floods it can bring. Last week one of those monsoons, powered by the remnants of Hurricane Norbert, produced floodwaters so strong they completely washed out a section of the I-15 Interstate north of town. With no road for several days, those traveling to and from Utah were forced to take a long detour, winding through nearby towns and wasting precious travel time.

An effective CDC solution for design rule checking can work much the same way, like a straight, clearly marked highway that quickly delivers you directly to your destination. Without such a solution, detouring past the many CDC issues that are becoming more pervasive in FPGA design can quickly become a long, winding road – and an inefficient use of time and resources. I covered some of these CDC nightmares in a previous article, and in this post I’ll share some best practices to help avoid these roadblocks. I’ll also demonstrate how new CDC rule plugins (to be added later this year to ALINT™) can help in the mitigation of such issues.

Read the rest of Averting CDC Roadblocks in FPGA Design

Simulate UVM & SystemVerilog online for free

 
August 19th, 2014 by Sunil Sahoo

Aldec-on-EDA-Playground-200-170During a recent trip to Austin, Texas, I spent some time with Aldec Partner, Victor Lyuboslavsky of Victor EDA and creator of the EDA Playground. Victor EDA is one of those organizations that Aldec aligns easily with because we share a strong commitment to accelerate learning within the engineering community by providing the right tools, training and resources.

As a result of this partnership, we are pleased to announce that Aldec Riviera-PRO EDU™ Advanced Verification Platform is now available on EDA Playground.

Here’s an excerpt from Victor’s recent guest blog post on the Aldec Design and Verification Blog, that illustrates how engineers can benefit from leveraging this tool to practice UVM & SystemVerilog simulation:

You may have found yourself among those eyeing the job market and wondering, “How hard is it to switch fields and become a verification engineer?”

Read the rest of Simulate UVM & SystemVerilog online for free

FPGA-Based Prototyping Q&A: 100 Million Gates and Beyond

 
July 30th, 2014 by Krzysztof Szczur

live-aldec-webinar

I am a Hardware Technical Support Manager. Ask Me Anything!

Earlier this summer, I joined a team traveling from Aldec’s R&D offices in Kraków, Poland to attend the annual Design Automation Conference (DAC) in San Francisco. As Technical Support Manager for Aldec’s Hardware Products Division, my goals for this event were two-fold. First, as we’ve made huge enhancements to our HES-7™ FPGA prototyping solution in the past year, I wanted to be there in person to share more about them in demos and presentations at the Aldec booth.

Secondly, and really my favorite part of DAC, I wanted to hear from engineers in the field looking for solutions to their real-world problems. Sometimes I have immediate answers for their questions, like the engineer who was not happy with their current solution’s implementation time or the fellow that needed support for in-house development boards. Occasionally though, I don’t have an immediate answer and instead they’ve given me valuable ideas that I get to take back home to my team so we can set to work developing solutions.

Read the rest of FPGA-Based Prototyping Q&A: 100 Million Gates and Beyond

Stress-Relief for Requirements-Based Verification

 
July 16th, 2014 by Louie De Luna

DO-254-RequirementsIf they’re being honest, anyone who has verified an FPGA under strict DO-254 guidance will tell you that it is stressful. Show me an engineer on their first DO-254 project – and I’ll show you someone pulling out their hair and downing what is probably their 5th cup of coffee while these important questions weigh heavy on their minds:

Have we reviewed all FPGA requirements and validated derived FPGA requirements? Do we have a good record of the review activities?

Do I have a test for each functional FPGA requirement? What’s the status of the tests? How do I track the progress and document the results?

Read the rest of Stress-Relief for Requirements-Based Verification

DO-254/CTS™ solves Elbit’s major challenges

 
June 24th, 2014 by Louie De Luna

Blog_img_062414Aldec has been working closely with Elbit Systems in Israel on an important DO-254 project for some time now. Using Aldec’s specialized solution DO-254/CTS™ as their primary FPGA physical testing platform, Elbit recently passed a critical EASA verification audit for DO-254/ED-80 DAL A FPGAs.

As a DO-254 evangelist, I have long recognized the value and benefits of Aldec’s solution to the avionics industry, so it was particularly rewarding to hear these words from Moshe Porian, Logic Design Verification Group Leader at Elbit Systems Aerospace Division, “Aldec helped us solve several of our verification challenges. This is the first time in Elbit’s history that we have been able to bring more than 5 FPGA devices to the audit.”

DO-254/CTS solved Elbit’s major challenges, enabling them to test in hardware 100% of FPGA pin-level requirements. As opposed to developing software test vectors, Elbit used their simulation testbench as test vectors for FPGA at-speed testing which cut their development costs. For the rest of this article, visit the Aldec Design and Verification Blog.

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