Open side-bar Menu
 Aldec Design and Verification
Engineer Santa
Engineer Santa
Santa Claus, also known as Father Christmas, Sinterklaas or Sint Nicolaas, possesses centuries of experience in toy and product design. More recently, Santa obtained a master’s degree in computer engineering from North Pole University in order to keep pace with the increasing use of software in … More »

Looking for Practical Holiday Gift Ideas?

December 4th, 2014 by Engineer Santa

Happy Holidays! We’ve made it to Day 4 of Aldec’s #12DaysofUsefulGifts giveaway. If you’ve been keeping up with us on Twitter and YouTube, you know that we’ve given away some fun prizes already. But that’s just the beginning, the prizes will get larger each day until the contest ends on December 12th!

If you are looking for some practical and useful gift ideas for the holidays, take a look at some of the fun prizes we’ve already given away.

Day #1day-1_400 Day #2day-2_400
Professional Cleaning Set for DSLR Cameras

Air Vent Mount for Cell Phones

Winner! Jonathan S.

Miles Kimball Manual Hand Held Shredder

Bushnell Falcon 7×35 Binoculars with Case

Winner! Alan S.

Day #3day-3_400 Day #4day-4_400
Magisso Tea Cup

Grillight LED BBQ Spatula

Winner! Daniel H.

Sugru Hardware Sealer

Pocketmonkey Wallet Multi-Tool

Could be you! Enter today at

To enter Aldec’s #12DaysOfUsefulGifts drawing, visit There you will take a brief verification survey and automatically be entered to win. You only need to take the survey once to be eligible for daily drawings from Dec 1st-12th. You can also earn additional chances to win by sharing the contest link and viewing the daily contest video. Follow Aldec on Twitter where we will announce each day’s winner and unveil the next day’s prize. Good luck!


How HES™ Technology Solved Problems for These Users

October 20th, 2014 by Krzysztof Szczur

HES_USE_CASESRecognizing a problem that engineers are facing and developing a solution has been Aldec’s rather straight-forward mantra for going on thirty years now. Aldec launched its Hardware Emulation Solutions (HES) product in 2003, integrating RTL simulation with hardware emulation, and offering hardware and software design teams the ability to work concurrently. Today HES™ is a fully automated and scriptable HybridVerification and Validation environment for SoC and ASIC designs capable of bit-level simulation acceleration, SCE-MI 2.1 transaction emulation, hardware prototyping, and virtual modeling.

Read the rest of How HES™ Technology Solved Problems for These Users

Averting CDC Roadblocks in FPGA Design

September 19th, 2014 by Ajay Pradhan

Rough-RoadThis being my first summer in Las Vegas, it is the first time I’ve experienced the rainy, desert monsoon season and the powerful flash floods it can bring. Last week one of those monsoons, powered by the remnants of Hurricane Norbert, produced floodwaters so strong they completely washed out a section of the I-15 Interstate north of town. With no road for several days, those traveling to and from Utah were forced to take a long detour, winding through nearby towns and wasting precious travel time.

An effective CDC solution for design rule checking can work much the same way, like a straight, clearly marked highway that quickly delivers you directly to your destination. Without such a solution, detouring past the many CDC issues that are becoming more pervasive in FPGA design can quickly become a long, winding road – and an inefficient use of time and resources. I covered some of these CDC nightmares in a previous article, and in this post I’ll share some best practices to help avoid these roadblocks. I’ll also demonstrate how new CDC rule plugins (to be added later this year to ALINT™) can help in the mitigation of such issues.

Read the rest of Averting CDC Roadblocks in FPGA Design

Simulate UVM & SystemVerilog online for free

August 19th, 2014 by Sunil Sahoo

Aldec-on-EDA-Playground-200-170During a recent trip to Austin, Texas, I spent some time with Aldec Partner, Victor Lyuboslavsky of Victor EDA and creator of the EDA Playground. Victor EDA is one of those organizations that Aldec aligns easily with because we share a strong commitment to accelerate learning within the engineering community by providing the right tools, training and resources.

As a result of this partnership, we are pleased to announce that Aldec Riviera-PRO EDU™ Advanced Verification Platform is now available on EDA Playground.

Here’s an excerpt from Victor’s recent guest blog post on the Aldec Design and Verification Blog, that illustrates how engineers can benefit from leveraging this tool to practice UVM & SystemVerilog simulation:

You may have found yourself among those eyeing the job market and wondering, “How hard is it to switch fields and become a verification engineer?”

Read the rest of Simulate UVM & SystemVerilog online for free

FPGA-Based Prototyping Q&A: 100 Million Gates and Beyond

July 30th, 2014 by Krzysztof Szczur


I am a Hardware Technical Support Manager. Ask Me Anything!

Earlier this summer, I joined a team traveling from Aldec’s R&D offices in Kraków, Poland to attend the annual Design Automation Conference (DAC) in San Francisco. As Technical Support Manager for Aldec’s Hardware Products Division, my goals for this event were two-fold. First, as we’ve made huge enhancements to our HES-7™ FPGA prototyping solution in the past year, I wanted to be there in person to share more about them in demos and presentations at the Aldec booth.

Secondly, and really my favorite part of DAC, I wanted to hear from engineers in the field looking for solutions to their real-world problems. Sometimes I have immediate answers for their questions, like the engineer who was not happy with their current solution’s implementation time or the fellow that needed support for in-house development boards. Occasionally though, I don’t have an immediate answer and instead they’ve given me valuable ideas that I get to take back home to my team so we can set to work developing solutions.

Read the rest of FPGA-Based Prototyping Q&A: 100 Million Gates and Beyond

Stress-Relief for Requirements-Based Verification

July 16th, 2014 by Louie De Luna

DO-254-RequirementsIf they’re being honest, anyone who has verified an FPGA under strict DO-254 guidance will tell you that it is stressful. Show me an engineer on their first DO-254 project – and I’ll show you someone pulling out their hair and downing what is probably their 5th cup of coffee while these important questions weigh heavy on their minds:

Have we reviewed all FPGA requirements and validated derived FPGA requirements? Do we have a good record of the review activities?

Do I have a test for each functional FPGA requirement? What’s the status of the tests? How do I track the progress and document the results?

Read the rest of Stress-Relief for Requirements-Based Verification

DO-254/CTS™ solves Elbit’s major challenges

June 24th, 2014 by Louie De Luna

Blog_img_062414Aldec has been working closely with Elbit Systems in Israel on an important DO-254 project for some time now. Using Aldec’s specialized solution DO-254/CTS™ as their primary FPGA physical testing platform, Elbit recently passed a critical EASA verification audit for DO-254/ED-80 DAL A FPGAs.

As a DO-254 evangelist, I have long recognized the value and benefits of Aldec’s solution to the avionics industry, so it was particularly rewarding to hear these words from Moshe Porian, Logic Design Verification Group Leader at Elbit Systems Aerospace Division, “Aldec helped us solve several of our verification challenges. This is the first time in Elbit’s history that we have been able to bring more than 5 FPGA devices to the audit.”

DO-254/CTS solved Elbit’s major challenges, enabling them to test in hardware 100% of FPGA pin-level requirements. As opposed to developing software test vectors, Elbit used their simulation testbench as test vectors for FPGA at-speed testing which cut their development costs. For the rest of this article, visit the Aldec Design and Verification Blog.

The 80s music at DAC was my idea. You’re welcome.

June 24th, 2014 by Sunil Sahoo

If you attended the Monday Night Reception at DAC 2014, you were greeted with a blast of 80s pop music. If you then said to yourself, “I’d like to meet the genius behind that idea” – that would be me. A few weeks before DAC, our marketing manager came to me with the task of being the DJ for the Monday night reception. As soon as I heard “DJ” I envisioned turntables, cool headphones, disco lights and all the fame that follows. My dreams were dashed a few moments later when she explained that I would only have a PA and a laptop.

Undaunted, I resolved to be the best DJ in the history of DAC Monday Night Networking Receptions. The first challenge was finding music everyone would enjoy. I naturally settled on 80s pop as my genre. I had the brilliant idea of picking a few songs from each year and playing it as a progressive 80s timeline during the evening. I changed my mind when I realized that bright idea would require some serious manual research and work.

Did I give up? Of course not. I did what any good engineer would do – I found an easy (and smart) solution that did not require substantial extra effort – a bit like re-using verification ip’s instead of making them from scratch. This level of engineering genius is often mistakenly perceived as laziness, but I like to call it being smart. In fact I recently wrote a blog on the topic of working smart not hard.

For the rest of this article, visit the Aldec Design and Verification Blog.

OS-VVM CoveragePkg, A Detailed Example

May 15th, 2014 by Satyam Jani

Alex Grove, FirstEDA Applications Specialist, was kind enough to author a guest blog for Aldec. Here’s an excerpt:

Here in Europe, I recently had the opportunity to work with Jim Lewis, OS-VVM Chief Architect and IEEE 1076 Working Group Chair, on the first Advanced VHDL Testbenches & Verification training course. This training, held in Bracknell, UK, was attended by engineers from several major European system companies who design and verify programmable devices (FPGAs). VHDL is by far the dominate language used by Europe’s system companies for the design and verification of FPGAs, however it is unclear to many how to enhance their verification with VHDL. What I have found is that experienced FPGA design engineers (including myself) are not utilising the VHDL language for verification.

Jim Lewis introduces VHDL’s verification capabilities, including new VHDL 2008 features and the Open Source VHDL Verification Methodology (OSVVM). OSVVM provides a methodology for testbench development and verification packages that provide functional coverage and random value generation. Read the rest of OS-VVM CoveragePkg, A Detailed Example

See the Future with Impact Analysis

April 9th, 2014 by Louie De Luna

Imagine if you could look into the future…

–   See the impact of requirements changes before they occur.

–   Know with certainty which lines of code in an HDL design or testbench file needed to be re-evaluated based on a change request.

–   Understand how a requirement change impacts the project schedule to help plan and allocate resources effectively.

Impact Analysis Defined

Seeing the future is possible with Impact Analysis, a practice within the change control process of product development. Impact Analysis provides information on what design and verification elements, artifacts, hardware components and materials, personnel, assets or activities that may be affected due to a requirement change. Armed with Impact Analysis data, you can then determine which elements to re-evaluate, modify, and even re-create if necessary.

Read the rest of See the Future with Impact Analysis

S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy