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 Aldec Design and Verification
Dr. Stanley M. Hyduke
Dr. Stanley M. Hyduke
Aldec Founder/CEO - Born in Poland, Dr. Hyduke received his Master of Science in Telecommunications Degree in 1962 from Technical University of Wroclaw, Poland and obtained his Doctorate from Kharkov Technical University in Ukraine. Dr. Hyduke held positions at EDO Commercial Corporation, Control … More »

Aldec Verification Tools Implement the ASIC Verification Flow

 
May 10th, 2016 by Dr. Stanley M. Hyduke

Aldec-Verification-SpectrumAldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability of FPGAs have increased, however, the distinction between FPGA and ASIC design has narrowed. A modern FPGA verification flow looks very much like an ASIC verification flow.

Small and large fabless companies alike need a reliable verification partner that suits their budgets while still providing a high level of support. To answer the call, we at Aldec have extended our spectrum of verification tools for use in digital ASIC designs.

A Basic ASIC Verification Flow

Managing verification for ASICs requires a well-defined verification plan.  Efficient verification planning starts with functional and design requirements in which requirements are mapped to verification methods, scenarios, goals and metrics, coverage groups, and results. Mapping entails traceability throughout the project that must be well maintained so that changes in the requirements will seamlessly reflect potential changes downstream to the elements of the verification plan.

While traceability can benefit any design, it is mandatory for safety-critical designs regulated by standards such as ISO-26262 for automotive, IEC-61508 for industrial and DO-254 for avionics.
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UVM Register Layer: The Structure

 
April 6th, 2016 by Henry Chan

UVM-Register-Layer-The-StructureI don’t know about you, but I am looking forward to the day where we won’t even have to go to the doctor’s office for an exam. Instead, we will all have scanners in our homes that will transmit full digital models to our doctors who can then poke, prod, and examine us remotely.

This is essentially what the UVM register layer allows and does. The UVM register layer acts similarly by modeling and abstracting registers of a design. It attempts to mirror the design registers by creating a model in the verification testbench. By applying stimulus to the register model, the actual design registers will exhibit the changes applied by the stimulus.

The benefit of this approach comes from the high level of abstraction provided. The bus protocols for accessing registers can change from design to design, but any stimulus developed for verification of the registers doesn’t have to. This makes it easy to port code from one project to the next if the registers are the same. Taking a look at Fig. 1 provides a better understanding of what a register model implementation might look like with respect to the UVM environment.
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Acceleration-Ready UVM Webinar with Doulos and Aldec

 
April 6th, 2016 by Krzysztof Szczur

doulos_logo

Doulos CTO, John Aynsley, and I will be presenting a free 1 hour training  webinar, Acceleration-Ready UVM, on Wednesday April 13th, 2016. Learn more in this guest blog by John Aynsley, excerpted from the Aldec Design and Verification Blog.

Acceleration-Ready UVM 

by Doulos CTO, John Aynsley

We hear that emulation is one of the fastest-growing segments in EDA right now, yet simulation still continues to be the main workhorse for functional verification, and SystemVerilog and UVM are everywhere you look. But how do you combine the two? How do you run a UVM-based constrained random verification environment alongside an emulator and get reasonable execution speed?

Many vendors have solutions, including Aldec with their HES-DVM™ emulator. Their solution is based on the Accellera SCE-MI standard, and in particular on SV-Connect, which is a function-based interface that uses the SystemVerilog DPI (Direct Programming Interface) to pass information between the host and the emulator. You partition your UVM drivers and monitors into two parts, a small proxy that remains on the host and a synthesizable implementation that goes into the emulator. That way, all of the low-level timing detail is removed from the UVM code running on the host and is placed in the emulator, where it belongs. The communication between the host and the emulator can be optimized to avoid the emulator being stalled while waiting for the slower UVM simulation running on the host.

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Why I see C in SCE-MI

 
March 18th, 2016 by Jacek Majkowski

blog_img_scemi_022416The two questions I hear most often while doing presentations about SCE-MI transaction based emulation are “Can we have coffee break?” and “Why do we need a thin C layer between two SystemVerilog tops”?

You a probably reading this during a coffee break, so let’s jump to second question. It refers to this diagram showing how to connect a SystemVerilog testbench (usually UVM) with DUT in SystemVerilog using a DPI transactor, as defined by the Function-based.

blog_img_scemi_01

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UVM. It’s Organized and Systematic.

 
February 10th, 2016 by Henry Chan

The-fundamentals-of-UVMOne of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to keep the basics of UVM engrained in your brain. You always want a good foundation and development of strong fundamentals in any endeavor. Verification is no different and UVM hammers the fundamentals home.

UVM has a great structure and organization paradigm. I consider there to be two distinct and fundamental elements in the UVM structure: Components and Objects. Now this characterization isn’t strictly correct because uvm_components are extended from uvm_objects, but I think they are used in such a way that warrants the distinction. I consider it similar to the idea of trucks and cars. In my view, trucks are also cars, but it’s useful to note the difference.

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Reprogrammable, reprogrammable, reprogrammable: What’s great about FPGAs!

 
January 22nd, 2016 by Alex Grove, Applications Specialist at FirstEDA

I-loveFPGAsI like FPGAs. My first experience with an FPGA was my university final year project where I demonstrated BIST with four Xilinx© 3000 devices; this was before FPGAs had JTAG built in. Filling up these devices with ViewDraw schematics required many hours in front of a terminal.   Fast track to today’s advances such as Xilinx UltraScale and Vivado HLx, and I hope you would agree things have moved on quite a bit.

Amid all this changes, however, there are some things that have remained constant. Those are the three things that are great about FPGAs: they are reprogrammable, reprogrammable, and, they are reprogrammable!

So how is this capability utilized? Here are three examples:

Electronic products using FPGAs:

I think it is important not look at FPGAs as some poor cousin of an ASIC. This view is from the days of LSI Logic and Xilinx marketing battles, when FPGAs were used for mopping up “glue logic”. Today an FPGA provides a massively parallel programmable digital platform with a lot of silicon IP, such as high-performance interfaces. This capability is widely used by many industries now; it is not solely driven by the volume of parts. Today, you even find FPGAs in consumer products.

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Verifying Large FPGAs Isn’t Easy

 
December 15th, 2015 by Satyam Jani

FPGA designers using VHDL have three choices: Stick with VHDL, switch to SystemVerilog, or.. use the best of both. This guest blog from Doug Perry, Senior Member Technical Staff at Doulos, outlines the pros and cons of each.

The latest crop of FPGA devices are enormous when compared to ASICs that were built not that long ago. Verifying these ASICs required detailed plans, multiple tools, and sometimes special languages. Verification was key because the cost of a respin was prohibitive.  FPGA designers using VHDL have three choices: Stick with VHDL, switch to SystemVerilog, or.. use the best of both. This guest blog from Doug Perry, Senior Member Technical Staff at Doulos, outlines the pros and cons of each.

The same is not necessarily true of FPGAs because they can simply be re-programmed when an error is found. However the cost of finding the error in the lab can still be very expensive. This is related to the fact that the number of LUTs available in the device has skyrocketed, but the number of IO pins has not. Therefore getting visibility into the inner workings of the device from outside becomes much more difficult. Finding the source of an error therefore also becomes increasingly difficult. To counteract this problem, designers need to find errors before the device gets into the lab. To do this they need to adopt ASIC-like verification methodologies.

U.V.M. Spells Relief

 
December 4th, 2015 by Henry Chan

blog_120215Verification can be a challenging endeavor. As designs grow in size and complexity, engineers are having difficulty confirming their designs behave properly. This is where UVM may provide some relief. UVM aims to deliver an easier and more flexible way of creating robust test environments so that you can verify those difficult designs effortlessly.

So what is UVM?

UVM stands for universal verification methodology and is based on an earlier verification methodology (OVM 2.1.1 developed by Cadence and Mentor Graphics). Accellera used this OVM base, continued development, and now maintains it as a more modern and updated version in UVM. Tangibly, UVM is a library of SystemVerilog code that is intended to help engineers write effective test and verification environments. You can download the UVM class library code, user guide, and reference documents from Accellera’s website.

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‘UVM Really is Everywhere’ at DVCon Europe

 
November 4th, 2015 by Krzysztof Szczur
Next week, Aldec will join other top tier organizations as a proud Silver Sponsor at DVCon Europe 2015 in Munich, Germany. There our team will offer live demonstrations of hardware-assisted verification of UVM following Doulos Ltd.’s Easier UVM guidelines. Alex Grove of Aldec will also deliver a DVCon Europe tutorial, ‘UVM Hardware Assisted Acceleration with FPGA Co-emulation’.

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‘Don’t Be Afraid of UVM’ Webinar on YouTube

 
October 27th, 2015 by Sunil Sahoo

uvm_img_102715Just in time for Halloween, Aldec has released a popular past webinar Don’t be Afraid of UVM for Hardware Designers on YouTube.

Designers are usually very busy doing their work and have little time left for experimentation with new methodologies. Unfortunately for them, official documentation of UVM (Universal Verification Methodology) was written by Verification Engineers for Verification Engineers, concentrating on high-level features and completely neglecting lower-level details such as connecting UVM testbench to your design.

Our webinar starts with solid review of SystemVerilog interfaces with special attention paid to Virtual Interfaces. Then it proceeds to Sequences and other Data Items, processed by Sequencers and fed to the design under test via Drivers. The role of Monitors and Scoreboards in analysis of results is explained. The presentation concludes with environment configuration and running test from the top-level module.

For the rest of this article, visit the Aldec Design and Verification Blog.




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