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 Aldec Design and Verification

Archive for the ‘Functional Verification’ Category

U.V.M. Spells Relief

Friday, December 4th, 2015

blog_120215Verification can be a challenging endeavor. As designs grow in size and complexity, engineers are having difficulty confirming their designs behave properly. This is where UVM may provide some relief. UVM aims to deliver an easier and more flexible way of creating robust test environments so that you can verify those difficult designs effortlessly.

 

So what is UVM?

UVM stands for universal verification methodology and is based on an earlier verification methodology (OVM 2.1.1 developed by Cadence and Mentor Graphics). Accellera used this OVM base, continued development, and now maintains it as a more modern and updated version in UVM. Tangibly, UVM is a library of SystemVerilog code that is intended to help engineers write effective test and verification environments. You can download the UVM class library code, user guide, and reference documents from Accellera’s website.

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‘UVM Really is Everywhere’ at DVCon Europe

Wednesday, November 4th, 2015
Next week, Aldec will join other top tier organizations as a proud Silver Sponsor at DVCon Europe 2015 in Munich, Germany. There our team will offer live demonstrations of hardware-assisted verification of UVM following Doulos Ltd.’s Easier UVM guidelines. Alex Grove of Aldec will also deliver a DVCon Europe tutorial, ‘UVM Hardware Assisted Acceleration with FPGA Co-emulation’.

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‘Don’t Be Afraid of UVM’ Webinar on YouTube

Tuesday, October 27th, 2015

uvm_img_102715Just in time for Halloween, Aldec has released a popular past webinar Don’t be Afraid of UVM for Hardware Designers on YouTube.

Designers are usually very busy doing their work and have little time left for experimentation with new methodologies. Unfortunately for them, official documentation of UVM (Universal Verification Methodology) was written by Verification Engineers for Verification Engineers, concentrating on high-level features and completely neglecting lower-level details such as connecting UVM testbench to your design.

Our webinar starts with solid review of SystemVerilog interfaces with special attention paid to Virtual Interfaces. Then it proceeds to Sequences and other Data Items, processed by Sequencers and fed to the design under test via Drivers. The role of Monitors and Scoreboards in analysis of results is explained. The presentation concludes with environment configuration and running test from the top-level module.

For the rest of this article, visit the Aldec Design and Verification Blog.

The Pythonic Tonic: Miracle cure or Snake-oil?

Wednesday, May 20th, 2015

python-logoPython is making inroads in the EDA landscape, but is all the hype justified? Do the productivity benefits of a dynamic language translate to gains for real-world development for ASIC and FPGA designs? Chris Higgs of Potential Ventures will be onsite at DAC to share his experiences using Python and Aldec Riviera-PRO to take products from idea to production quickly.

Chris recently wrote a Guest Blog on the topic, visit the Aldec Design Verification Blog to learn more.

So, what does a vendor-independent simulator look like?

Friday, May 15th, 2015

blog_independent_simulator_051515Well, the short answer to that is, “Awesome”. Perhaps, as the product manager of a simulation tool, I’m a little biased. Not to discount the challenges that FPGA design teams face on daily basis, particularly with device complexities now going through the roof.

There was a time, not so long ago, when using a single FPGA device from one vendor was not so uncommon and simulation and verification were quite interchangeable terms. However in recent years, with the development of more complex FPGAs and an even more complex design process involving the use of IPs, VIPs and third party models , the need for vendor agnostic tools for simulation and verification has become more evident.

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Are Metastability Monsters Lurking Beneath the Surface?

Thursday, March 5th, 2015

taming-mestastability-monstersEvery engineer and technician is aware of Murphy’s Law: “Anything that can go wrong will go wrong”.

The law appears when your elegantly-sculpted hardware and artfully-styled software code bang up against the real world of transition delays and timing requirements.

Over time, designers and trouble-shooters develop a healthy respect for Mr. Murphy and begin to anticipate when he is looking over their shoulder, learning “best practices” for recurring design problems.

The toughest design problems to trouble-shoot are ones that fail intermittently. A hidden flaw seems to pop up randomly with no certain pattern or definable cause.

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Xilinx Tcl Store Integrates Aldec Simulators with Vivado IDE

Tuesday, February 24th, 2015

Xilinx-Tcl-StoreTaking a cue from the open-source community, Xilinx has launched a Tcl Store that aggregates Tcl scripts contributed by the greater development community to expand the capabilities of the Vivado® Integrated Design Environment.

All Tcl scripts contributed to the Xilinx repository are free and re-distributable under an open-source license that is based on the Berkeley Source Distribution (BSD) model. Vivado users can now download apps from the Tcl Store that include practical bundles of Tcl scripts that act just like Vivado commands, including an app that can integrate Aldec Active-HDL and Riviera-PRO tools within the Vivado design flow.

To take advantage of these pre-packaged Tcl Script apps within Vivado, users can access the Tcl Store via the Vivado IDE “Tools” menu. For the rest of this article, visit the Aldec Design and Verification Blog.

What inspired you to become an engineer?

Tuesday, February 24th, 2015

This week, February 22-28, we celebrate National Engineers Week in the US to recognize the contributions to society that engineers make. During this time, there is added emphasis in schools on the importance of learning math, science, and technical skills.

I work with Generation STEAM, a group organized by the SYN Shop MakerSpace and the Henderson district library to create a series of STEM (Science, Technology, Engineering, [Art], and Math) classes that are free to the public. For my part, I’ve had the privilege of teaching a basic electronics class for kids a few Saturdays this year – and it’s been a blast. Our hope is that we are encouraging a few young people to follow the path of engineering.

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Last call from Engineer Santa. Survey & daily drawings end Dec 12.

Thursday, December 11th, 2014

Well folks, last call from Engineer Santa. Aldec’s #12DaysofUsefulGifts giveaway will end this Friday, December 12 at 12pm midnight Pacific Standard Time.[preview_cut]

If you haven’t registered yet, you’ll want to hurry and visit www.aldec.com/survey. There you will take a brief verification survey and be entered to win.

If you’ve been keeping up with us on Twitter and YouTube, you know that we’ve given away some fun prizes already. If you are looking for some practical and useful gift ideas for the holidays, you might want to take a closer look. I’ve already talked about some of these from Days #1-4. We’ve given away more prizes since then and sent them to engineers all over the globe! Here, take a look…

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Looking for Practical Holiday Gift Ideas?

Thursday, December 4th, 2014

Happy Holidays! We’ve made it to Day 4 of Aldec’s #12DaysofUsefulGifts giveaway. If you’ve been keeping up with us on Twitter and YouTube, you know that we’ve given away some fun prizes already. But that’s just the beginning, the prizes will get larger each day until the contest ends on December 12th!

If you are looking for some practical and useful gift ideas for the holidays, take a look at some of the fun prizes we’ve already given away.

Day #1day-1_400 Day #2day-2_400
Professional Cleaning Set for DSLR Cameras

Air Vent Mount for Cell Phones

Winner! Jonathan S.

Miles Kimball Manual Hand Held Shredder

Bushnell Falcon 7×35 Binoculars with Case

Winner! Alan S.

Day #3day-3_400 Day #4day-4_400
Magisso Tea Cup

Grillight LED BBQ Spatula

Winner! Daniel H.

Sugru Hardware Sealer

Pocketmonkey Wallet Multi-Tool

Could be you! Enter today at

www.aldec.com/survey

 

To enter Aldec’s #12DaysOfUsefulGifts drawing, visit www.aldec.com/survey. There you will take a brief verification survey and automatically be entered to win. You only need to take the survey once to be eligible for daily drawings from Dec 1st-12th. You can also earn additional chances to win by sharing the contest link and viewing the daily contest video. Follow Aldec on Twitter where we will announce each day’s winner and unveil the next day’s prize. Good luck!

 

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