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 Aldec Design and Verification
Radek Nawrot
Radek Nawrot
Radek is a software product manager at Aldec, responsible for Active-HDL and Riviera-PRO product lines. He has over 7 years of experience in design and verification, including his role in the R&D division of Aldec in Europe. Radek hold his M.S. in Electronic and Communication Engineering from … More »

Beer, Cars, and Verification. My thoughts after DVCon Europe

November 9th, 2016 by Radek Nawrot

DVCon-Europe-AldecAs I write this, I am visiting the Aldec corporate office in the US on the day following their historical presidential election. It’s been a busy travel season for this product manager, and only a few weeks ago I was at DVCon Europe in Munich – the city of pork knuckles, beer… and of course, cars.

Munich-DVCon-EuropeThe DVCon Europe conference is certainly growing, and the methodology presented yearly continues to be more mature and ready to use. This year’s DVCon Europe was not thematically different from other conferences. Subjects like Automotive and IoT have flourished these past few years.

Yet, nowhere else like here in the heart of Bavaria has the discussion about cars acquired such importance. In this region known as the European Detroit, cars are a secular religion.

A few years ago we were wondering… how? Two years ago… when? Today production has its hands full and engineers are simply wondering… what’s next?

As with the American election, there is a sense that we are awaiting another revolution. Within a few dozen years, internal combustion engines will become extinct like dinosaurs, or become as Juergen Weyer of NXP has said, like “Kodak in the era of digital photography”.

And so we turn to the electronics field as the main solution for this new era. With this turn, ahead of us opens up new challenges related to design and testing, not to mention the safety of billions of users.

In the vastness of topics such as Automotive and IoT, I would not want us to miss this nugget from this year’s DVCon Europe Conference: UVVM, VHDL’s long-awaited alternative to UVM. With the large presence of VHDL in Europe, Universal VHDL Verification Methodology (UVVM) could not have been born anywhere else. The concept is based on the Bus Functional Model enriched by the favor of the well-known and liked OSVVM… and it promises to be interesting.

To learn more, we encourage you to register to attend an upcoming joint webinar with Bitvis, UVVM – A game changer for FPGA VHDL Verification, on Thursday, November 17. You can register for a time that’s convenient for you in the US or Europe.

 Fig1. Typical configuration of UVVM test environment. (Source Bitvis)

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Categories: Active-HDL, FPGA Design Creation and Simulation

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