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Krzysztof Szczur
Krzysztof Szczur
Krzysztof Szczur is a Hardware Technical Support Manager. He joined Aldec in 2001 and was a key member of the team that developed HES™, Aldec's FPGA-based co-simulation and emulation technology. He has worked in the fields of HDL IP-cores verification, testbench automation and design verification … More »

To Emulate or Prototype?

May 23rd, 2016 by Krzysztof Szczur

Emulation-or-PrototypingRecently I read a Semiwiki article, Army of Engineers on Site Only Masks Weakness, in which author Jean-Marie Brunet of Mentor Graphics wrote that FPGA Prototyping requires an army of tech support engineers on-site to mask the weaknesses of FPGA prototyping flows. As the Tech Support Manager for Aldec Hardware Emulation Solutions, I have to admit I’ve never had to deploy an army onsite.

It is true that FPGA Prototyping is more challenging than emulation. Yet, for the time invested in prototype setup, developers are rewarded with a validation platform that is capable of running orders of magnitude faster than emulation.

Emulation also has its benefits that appeal especially to design verification engineers. Aside from the completely automated compilation and setup flow, it offers robust debugging capabilities and a plethora of interfaces that connect the emulator with various verification environments like HDL Simulators, Virtual Platforms, model based design tools (e.g. Matlab and Simulink) or any other environment capable of C/C++ linking.

But wait, do you really need to choose between Emulation and Prototyping?

This may have been true in the 1990s, but a lot has changed since then. FPGA technology has evolved and matured as well as FPGA vendor’s synthesis and place & route software. For some reason however, the big-three of EDA keep it separate. The emulation hardware that is based on custom processors or custom FPGAs is extremely expensive and later, if you need to do prototyping for your design bring-up and firmware development, you wind up with investing more in FPGA-based hardware.

The engineers at Aldec have been working persistently to bridge this gap and unify a hardware platform to be used for both emulation and prototyping. They have developed HES-DVM™, which has evolved over the years to deliver the most cost effective solution.

This effectiveness comes from reusability and scalability.

HES-7™  is the latest generation of prototyping boards that contains largest Virtex®-7 and now Virtex UltraScale™ FPGAs from Xilinx®. These boards are available in various configurations including the backplane board that delivers the ability to scale the whole system up to 633 million ASIC gates (24 Virtex UltraScale 440 chips). The hardware is precisely designed to meet the most restrictive prototyping criteria for clocks distribution or signal integrity. We’ll have the actual boards at our Design Automation Conference (DAC) Booth #619 this year. Please visit to register for a hardware presentation and talk to me personally.

For the rest of this article, visit the Aldec Design and Verification Blog.

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Categories: Emulation/Acceleration, SoC and ASIC Prototyping

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